3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * Based on include/configs/yosemite.h
6 * (C) Copyright 2005-2007
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * SPDX-License-Identifier: GPL-2.0+
13 * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module
19 * High Level Configuration Options
21 #define CONFIG_440GR 1 /* Specific PPC440GR support */
22 #define CONFIG_HOSTNAME gdppc440etx
23 #define CONFIG_440 1 /* ... PPC440 family */
24 #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
26 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
29 * Include common defines/options for all AMCC eval boards
31 #include "amcc-common.h"
33 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/
34 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
37 * Base addresses -- Note these are effective addresses where the
38 * actual resources get mapped (not physical addresses)
40 #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
41 #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
42 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
43 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
44 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
46 /*Don't change either of these*/
47 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */
48 /*Don't change either of these*/
50 #define CONFIG_SYS_USB_DEVICE 0x50000000
51 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
54 * Initial RAM & stack pointer (placed in SDRAM)
56 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/
57 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
58 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
59 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
60 - GENERATED_GBL_DATA_SIZE)
61 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
66 #define CONFIG_CONS_INDEX 2 /* Use UART1 */
67 #define CONFIG_SYS_NS16550_SERIAL
68 #define CONFIG_SYS_NS16550_REG_SIZE 1
69 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
70 #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
74 * Define here the location of the environment variables (FLASH or EEPROM).
75 * Note: DENX encourages to use redundant environment in FLASH.
77 #define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/
82 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/
83 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
84 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/
86 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
87 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */
89 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/
90 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/
92 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/
94 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
96 #ifdef CONFIG_ENV_IS_IN_FLASH
97 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/
98 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
99 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */
101 /* Address and size of Redundant Environment Sector */
102 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
103 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
104 #endif /* CONFIG_ENV_IS_IN_FLASH */
109 #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/
110 #define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */
111 #define CONFIG_SYS_SDRAM_BANKS (2)
113 #define CONFIG_SDRAM_BANK0
114 #define CONFIG_SDRAM_BANK1
116 #define CONFIG_SYS_SDRAM0_TR0 0x410a4012
117 #define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000
118 #define CONFIG_SYS_SDRAM0_RTR 0x04080000
119 #define CONFIG_SYS_SDRAM0_CFG0 0x80000000
121 #undef CONFIG_SDRAM_ECC
126 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
129 * Default environment variables
131 #define CONFIG_EXTRA_ENV_SETTINGS \
132 CONFIG_AMCC_DEF_ENV \
133 CONFIG_AMCC_DEF_ENV_POWERPC \
134 CONFIG_AMCC_DEF_ENV_NOR_UPD \
135 "kernel_addr=fc000000\0" \
136 "ramdisk_addr=fc180000\0" \
139 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
140 #define CONFIG_PHY_ADDR 1
141 #define CONFIG_PHY1_ADDR 3
144 #define CONFIG_PANIC_HANG
148 * Commands additional to the ones defined in amcc-common.h
150 #define CONFIG_CMD_PCI
151 #undef CONFIG_CMD_EEPROM
158 #define CONFIG_PCI /* include pci support */
159 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
160 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
161 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/
162 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \
163 CONFIG_SYS_PCI_MEMBASE*/
165 /* Board-specific PCI */
166 #define CONFIG_SYS_PCI_TARGET_INIT
167 #define CONFIG_SYS_PCI_MASTER_INIT
169 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
170 #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */
173 * External Bus Controller (EBC) Setup
175 #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
177 /* Memory Bank 0 (NOR-FLASH) initialization */
178 #define CONFIG_SYS_EBC_PB0AP 0x03017200
179 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000)
181 #endif /* __CONFIG_H */