1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012 Atmel Corporation
4 * Copyright (C) 2019 Stefan Roese <sr@denx.de>
6 * Configuation settings for the GARDENA smart Gateway (AT91SAM9G25)
13 #include <linux/bitops.h>
16 /* ARM asynchronous clock */
17 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
18 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
21 #define CONFIG_SYS_SDRAM_BASE 0x20000000
22 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
24 #define CONFIG_SYS_INIT_SP_ADDR \
25 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
28 #define CONFIG_SYS_MAX_NAND_DEVICE 1
29 #define CONFIG_SYS_NAND_BASE 0x40000000
30 #define CONFIG_SYS_NAND_DBW_8 1
32 #define CONFIG_SYS_NAND_MASK_ALE BIT(21)
34 #define CONFIG_SYS_NAND_MASK_CLE BIT(22)
35 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
36 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
39 #define CONFIG_SPL_MAX_SIZE 0x7000
40 #define CONFIG_SPL_STACK 0x308000
42 #define CONFIG_SPL_BSS_START_ADDR 0x20000000
43 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
44 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
45 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
47 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
49 #define CONFIG_SYS_MASTER_CLOCK 132096000
50 #define CONFIG_SYS_AT91_PLLA 0x20c73f03
51 #define CONFIG_SYS_MCKR 0x1301
52 #define CONFIG_SYS_MCKR_CSS 0x1302
54 #define CONFIG_SPL_NAND_RAW_ONLY
55 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
56 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
57 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
59 #define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
60 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO