2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Eric Schumann, Phytec Messatechnik GmbH
9 * Jon Smirl <jonsmirl@gmail.com>
12 * Eric Millbrandt, DEKA Research and Development Corporation
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #define CONFIG_BOARDINFO "galaxy5200"
39 * High Level Configuration Options
42 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
43 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
44 #define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
47 * Valid values for CONFIG_SYS_TEXT_BASE are:
48 * 0xFFF00000 boot high (standard configuration)
50 * 0x00100000 boot from RAM (for testing only) does not work
52 #ifdef CONFIG_galaxy5200_LOWBOOT
53 #define CONFIG_SYS_TEXT_BASE 0xFE000000
56 #ifndef CONFIG_SYS_TEXT_BASE
57 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
61 * Serial console configuration
63 #define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 -> */
64 /* define gps port conf. */
65 /* register later on to */
66 /* enable UART function! */
67 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
68 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
71 * Command line configuration.
73 #include <config_cmd_default.h>
75 #define CONFIG_CMD_DATE
76 #define CONFIG_CMD_DHCP
77 #define CONFIG_CMD_EEPROM
78 #define CONFIG_CMD_I2C
79 #define CONFIG_CMD_JFFS2
80 #define CONFIG_CMD_MII
81 #define CONFIG_CMD_NFS
82 #define CONFIG_CMD_SNTP
83 #define CONFIG_CMD_PING
84 #define CONFIG_CMD_ASKENV
85 #define CONFIG_CMD_USB
86 #define CONFIG_CMD_CACHE
87 #define CONFIG_CMD_FAT
89 #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
91 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
92 #define CONFIG_SYS_LOWBOOT 1
94 /* RAMBOOT will be defined automatically in memory section */
96 #define MTDIDS_DEFAULT "nor0=physmap-flash.0"
97 #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
98 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
103 #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
104 #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
105 /* even with bootdelay=0 */
106 #define CONFIG_BOOT_RETRY_TIME 120 /* Reset if no command is entered */
107 #define CONFIG_RESET_TO_RETRY
109 #define CONFIG_PREBOOT "echo;" \
110 "echo Welcome to U-Boot;"\
113 #define CONFIG_BOOTCOMMAND "go ff300004 0; go ff300004 2 2;" \
114 "bootm ff040000 ff900000 fffc0000"
115 #define CONFIG_BOOTARGS "console=ttyPSC0,115200"
116 #define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"
119 * IPB Bus clocking configuration.
121 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
122 #define CONFIG_SYS_XLB_PIPELINING 1
127 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
128 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
129 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
130 #define CONFIG_SYS_I2C_SLAVE 0x7F
131 #define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */
134 * EEPROM CAT24WC32 configuration
136 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
137 #define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
138 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
139 #define CONFIG_SYS_EEPROM_SIZE 4096
140 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
141 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
147 #define CONFIG_RTC_DS3231 1
148 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
151 * Flash configuration
154 #define CONFIG_SYS_FLASH_BASE 0xfe000000
156 * The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this
159 #define CONFIG_SYS_FLASH_SIZE 0x02000000
160 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
162 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
163 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
164 #define CONFIG_SYS_FLASH_EMPTY_INFO
165 #define CONFIG_SYS_MAX_FLASH_SECT 259 /* max num of sects on one chip */
166 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
167 /* (= chip selects) */
168 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
171 * Use hardware protection. This seems required, as the BDI uses hardware
172 * protection. Without this, U-Boot can't work with this sectors as its
173 * protection is software only by default.
175 #define CONFIG_SYS_FLASH_PROTECTION 1
178 * Environment settings
181 #define CONFIG_ENV_IS_IN_EEPROM 1
182 #define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
183 /* beginning of the EEPROM */
184 #define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
186 #define CONFIG_ENV_OVERWRITE 1
189 * SDRAM configuration
192 #define SDRAM_MODE 0x018D0000
193 #define SDRAM_EMODE 0x40090000
194 #define SDRAM_CONTROL 0x71500F00
195 #define SDRAM_CONFIG1 0x73711930
196 #define SDRAM_CONFIG2 0x47770000
201 #define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
202 /* bootloader or debugger config */
203 #define CONFIG_SYS_SDRAM_BASE 0x00000000
204 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
206 /* Use SRAM until RAM will be available */
207 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
209 /* End of used area in SPRAM */
210 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
212 /* Size in bytes reserved for initial data */
214 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
215 GENERATED_GBL_DATA_SIZE)
216 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
218 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
219 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
220 # define CONFIG_SYS_RAMBOOT 1
223 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
224 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
225 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
227 /* Chip Select configuration for NAND flash */
228 #define CONFIG_SYS_CS1_START 0x20000000
229 #define CONFIG_SYS_CS1_SIZE 0x90000
230 #define CONFIG_SYS_CS1_CFG 0x00025b00
232 /* Chip Select configuration for Epson S1D13513 */
233 #define CONFIG_SYS_CS3_START 0x10000000
234 #define CONFIG_SYS_CS3_SIZE 0x400000
235 #define CONFIG_SYS_CS3_CFG 0xffff3d10
238 * Ethernet configuration
240 #define CONFIG_MPC5xxx_FEC 1
241 #define CONFIG_MPC5xxx_FEC_MII100
242 #define CONFIG_PHY_ADDR 0x01
243 #define CONFIG_NO_AUTOLOAD 1
248 * GPS port configuration
252 * PSC1_0 -> AC97 SDATA out
253 * PSC1_1 -> AC97 SDTA in
254 * PSC1_2 -> AC97 SYNC out
255 * PSC1_3 -> AC97 bitclock out
256 * PSC1_4 -> AC97 reset out
272 * PSC3_0 -> USB_OE OE out
273 * PSC3_1 -> USB_TXN Tx- out
274 * PSC3_2 -> USB_TXP Tx+ out
276 * PSC3_4 -> USB_RXP Rx+ in
277 * PSC3_5 -> USB_RXN Rx- in
278 * PSC3_6 -> USB_PWR PortPower out
279 * PSC3_7 -> USB_SPEED speed out
280 * PSC3_8 -> USB_SUSPEND suspend
281 * PSC3_9 -> USB_OVRCURNT overcurrent in
287 * USB differential mode
293 * Ethernet 100Mbit with MD
304 * ETH_10 -> ETH Collision
310 * ETH_16 -> ETH Rxerr
321 * IrDA/USB 48MHz clock generated internally
324 * ATA chip selects on csb_4/5
325 * CSB_4 -> ATA_CS0 out
326 * CSB_5 -> ATA_CS1 out
329 * PSC3_4 is used as CS6
332 * PSC3_5 is used as CS7
338 * gpio_wkup_7 is GPIO
341 * gpio_wkup_6 is GPIO
344 #define CONFIG_SYS_GPS_PORT_CONFIG 0x0d75a162
347 * Miscellaneous configurable options
349 #define CONFIG_SYS_LONGHELP /* undef to save memory */
350 #define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
352 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
354 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
355 #if defined(CONFIG_CMD_KGDB)
356 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
359 #if defined(CONFIG_CMD_KGDB)
360 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
362 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
364 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
365 /* Print Buffer Size */
366 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
367 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
369 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
370 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
372 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
373 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
375 #define CONFIG_DISPLAY_BOARDINFO 1
377 #define CONFIG_SYS_HUSH_PARSER 1
378 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
380 #define CONFIG_CRC32_VERIFY 1
382 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
384 CONFIG_BOOTP_DNS2 | \
385 CONFIG_BOOTP_SEND_HOSTNAME )
387 #define CONFIG_VERSION_VARIABLE 1
390 * Various low-level settings
392 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
393 #define CONFIG_SYS_HID0_FINAL HID0_ICE
395 /* no burst access on the LPB */
396 #define CONFIG_SYS_CS_BURST 0x00000000
397 /* one deadcycle for the 33MHz statemachine */
398 #define CONFIG_SYS_CS_DEADCYCLE 0x33333331
400 #define CONFIG_SYS_BOOTCS_CFG 0x0002d900
401 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
402 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
404 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
409 #define CONFIG_USB_CLOCK 0x0001bbbb
411 #define CONFIG_PSC3_USB
412 #define CONFIG_USB_CONFIG 0x00000100
413 #define CONFIG_USB_OHCI
414 #define CONFIG_USB_STORAGE
417 * IDE/ATA stuff Supports IDE harddisk
419 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
420 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
421 #undef CONFIG_IDE_LED /* LED for ide not supported */
423 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
424 #define CONFIG_IDE_PREINIT
425 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
426 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
427 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
428 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
429 /* Offset for data I/O */
430 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
431 /* Offset for normal register accesses */
432 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
433 /* Offset for alternate registers */
434 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
435 /* Interval between registers */
436 #define CONFIG_SYS_ATA_STRIDE 4
437 #define CONFIG_ATAPI 1
439 /* we enable IDE and FAT support, so we also need partition support */
440 #define CONFIG_DOS_PARTITION 1
443 * Open Firmware flat tree
445 #define CONFIG_OF_LIBFDT 1
446 #define CONFIG_OF_BOARD_SETUP 1
448 #define OF_CPU "PowerPC,5200@0"
449 #define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
450 #define OF_SOC "soc5200@f0000000"
451 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2600"
453 #endif /* __CONFIG_H */