1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuration settings for the EXYNOS 78x0 based boards.
5 * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
6 * based on include/exynos7420-common.h
7 * Copyright (C) 2016 Samsung Electronics
8 * Thomas Abraham <thomas.ab@samsung.com>
11 #ifndef __CONFIG_EXYNOS78x0_COMMON_H
12 #define __CONFIG_EXYNOS78x0_COMMON_H
14 /* High Level Configuration Options */
15 #define CONFIG_SAMSUNG /* in a SAMSUNG core */
18 #include <asm/arch/cpu.h> /* get chip and board defs */
19 #include <linux/sizes.h>
21 /* Miscellaneous configurable options */
22 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
23 #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
25 /* Boot Argument Buffer Size */
26 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
28 /* Timer input clock frequency */
29 #define COUNTER_FREQUENCY 26000000
32 #define CONFIG_DEVICE_TREE_LIST "EXYNOS78x0-a5y17lte"
34 #define CPU_RELEASE_ADDR secondary_boot_addr
36 #define CONFIG_SYS_BAUDRATE_TABLE \
37 {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
39 #define CONFIG_BOARD_COMMON
41 #define CONFIG_SYS_SDRAM_BASE 0x40000000
42 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - GENERATED_GBL_DATA_SIZE)
43 /* DRAM Memory Banks */
44 #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
45 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
46 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
47 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
48 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
49 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
50 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
51 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
52 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
53 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
54 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
55 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
56 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
57 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
58 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
59 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
60 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
61 #define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
62 #define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE
63 #define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
64 #define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE
65 #define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
66 #define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE
67 #define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
68 #define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE
70 #ifndef MEM_LAYOUT_ENV_SETTINGS
71 #define MEM_LAYOUT_ENV_SETTINGS \
72 "bootm_size=0x10000000\0" \
73 "bootm_low=0x40000000\0"
76 #ifndef EXYNOS_DEVICE_SETTINGS
77 #define EXYNOS_DEVICE_SETTINGS \
83 #ifndef EXYNOS_FDTFILE_SETTING
84 #define EXYNOS_FDTFILE_SETTING
87 #define EXTRA_ENV_SETTINGS \
88 EXYNOS_DEVICE_SETTINGS \
89 EXYNOS_FDTFILE_SETTING \
90 MEM_LAYOUT_ENV_SETTINGS
92 #define CONFIG_EXTRA_ENV_SETTINGS \
95 #endif /* __CONFIG_EXYNOS78x0_COMMON_H */