1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013 Samsung Electronics
5 * Configuration settings for the SAMSUNG EXYNOS5 board.
8 #ifndef __CONFIG_EXYNOS5_COMMON_H
9 #define __CONFIG_EXYNOS5_COMMON_H
11 #include "exynos-common.h"
13 /* Power Down Modes */
14 #define S5P_CHECK_SLEEP 0x00000BAD
15 #define S5P_CHECK_DIDLE 0xBAD00000
16 #define S5P_CHECK_LPA 0xABAD0000
18 /* Offset for inform registers */
19 #define INFORM0_OFFSET 0x800
20 #define INFORM1_OFFSET 0x804
21 #define INFORM2_OFFSET 0x808
22 #define INFORM3_OFFSET 0x80c
24 /* select serial console configuration */
25 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
28 #define COPY_BL2_FNPTR_ADDR 0x02020030
30 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
31 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
32 #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
33 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
34 #define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
35 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
36 #define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
37 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
38 #define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
39 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
40 #define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
41 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
42 #define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
43 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
44 #define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
45 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
49 /* Ethernet Controllor Driver */
51 #define CFG_ENV_SROM_BANK 1
52 #endif /*CONFIG_CMD_NET*/
54 /* Enable Time Command */
59 #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
60 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
61 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
63 #define BOOT_TARGET_DEVICES(func) \
70 #include <config_distro_bootcmd.h>
72 #ifndef MEM_LAYOUT_ENV_SETTINGS
73 /* 2GB RAM, bootm size of 256M, load scripts after that */
74 #define MEM_LAYOUT_ENV_SETTINGS \
75 "bootm_size=0x10000000\0" \
76 "kernel_addr_r=0x42000000\0" \
77 "fdt_addr_r=0x43000000\0" \
78 "ramdisk_addr_r=0x43300000\0" \
79 "scriptaddr=0x50000000\0" \
80 "pxefile_addr_r=0x51000000\0"
83 #ifndef EXYNOS_DEVICE_SETTINGS
84 #define EXYNOS_DEVICE_SETTINGS \
90 #ifndef EXYNOS_FDTFILE_SETTING
91 #define EXYNOS_FDTFILE_SETTING
94 #define CFG_EXTRA_ENV_SETTINGS \
95 EXYNOS_DEVICE_SETTINGS \
96 EXYNOS_FDTFILE_SETTING \
97 MEM_LAYOUT_ENV_SETTINGS \
100 #endif /* __CONFIG_EXYNOS5_COMMON_H */