1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013 Samsung Electronics
5 * Configuration settings for the SAMSUNG EXYNOS5 board.
8 #ifndef __CONFIG_EXYNOS5_COMMON_H
9 #define __CONFIG_EXYNOS5_COMMON_H
11 #define CONFIG_EXYNOS5 /* Exynos5 Family */
13 #include "exynos-common.h"
15 #define CONFIG_EXYNOS_SPL
19 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
20 #define CONFIG_TRACE_EARLY_SIZE (8 << 20)
21 #define CONFIG_TRACE_EARLY
22 #define CONFIG_TRACE_EARLY_ADDR 0x50000000
25 /* Enable ACE acceleration for SHA1 and SHA256 */
26 #define CONFIG_EXYNOS_ACE_SHA
28 /* Power Down Modes */
29 #define S5P_CHECK_SLEEP 0x00000BAD
30 #define S5P_CHECK_DIDLE 0xBAD00000
31 #define S5P_CHECK_LPA 0xABAD0000
33 /* Offset for inform registers */
34 #define INFORM0_OFFSET 0x800
35 #define INFORM1_OFFSET 0x804
36 #define INFORM2_OFFSET 0x808
37 #define INFORM3_OFFSET 0x80c
39 /* select serial console configuration */
40 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
42 /* Thermal Management Unit */
43 #define CONFIG_EXYNOS_TMU
46 #define COPY_BL2_FNPTR_ADDR 0x02020030
47 #define CONFIG_SUPPORT_EMMC_BOOT
49 /* specific .lds file */
51 /* Boot Argument Buffer Size */
52 /* memtest works on */
53 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
54 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
55 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
59 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
60 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
61 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
62 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
63 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
64 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
65 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
66 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
67 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
68 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
69 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
70 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
71 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
72 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
73 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
74 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
76 #define CONFIG_SYS_MONITOR_BASE 0x00000000
78 #define CONFIG_SYS_MMC_ENV_DEV 0
80 #define CONFIG_SECURE_BL1_ONLY
82 /* Secure FW size configuration */
83 #ifdef CONFIG_SECURE_BL1_ONLY
84 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
86 #define CONFIG_SEC_FW_SIZE 0
89 /* Configuration of BL1, BL2, ENV Blocks on mmc */
90 #define CONFIG_RES_BLOCK_SIZE (512)
91 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
92 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
93 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
95 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
96 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
98 /* U-Boot copy size from boot Media to DRAM.*/
99 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
100 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
102 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
103 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
106 #define CONFIG_SYS_I2C_S3C24X0
107 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
108 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
112 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
113 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
114 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
115 #define CONFIG_ENV_SPI_BUS 1
116 #define CONFIG_ENV_SPI_MAX_HZ 50000000
119 /* Ethernet Controllor Driver */
120 #ifdef CONFIG_CMD_NET
121 #define CONFIG_ENV_SROM_BANK 1
122 #endif /*CONFIG_CMD_NET*/
124 /* Enable Time Command */
129 #define CONFIG_USB_BOOTING
130 #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
131 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
132 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
134 #define BOOT_TARGET_DEVICES(func) \
141 #include <config_distro_bootcmd.h>
143 #ifndef MEM_LAYOUT_ENV_SETTINGS
144 /* 2GB RAM, bootm size of 256M, load scripts after that */
145 #define MEM_LAYOUT_ENV_SETTINGS \
146 "bootm_size=0x10000000\0" \
147 "kernel_addr_r=0x42000000\0" \
148 "fdt_addr_r=0x43000000\0" \
149 "ramdisk_addr_r=0x43300000\0" \
150 "scriptaddr=0x50000000\0" \
151 "pxefile_addr_r=0x51000000\0"
154 #ifndef EXYNOS_DEVICE_SETTINGS
155 #define EXYNOS_DEVICE_SETTINGS \
161 #ifndef EXYNOS_FDTFILE_SETTING
162 #define EXYNOS_FDTFILE_SETTING
165 #define CONFIG_EXTRA_ENV_SETTINGS \
166 EXYNOS_DEVICE_SETTINGS \
167 EXYNOS_FDTFILE_SETTING \
168 MEM_LAYOUT_ENV_SETTINGS \
171 #endif /* __CONFIG_EXYNOS5_COMMON_H */