1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * egnite GmbH <info@egnite.de>
6 * Configuation settings for Ethernut 5 with AT91SAM9XE.
12 #include <asm/hardware.h>
14 /* The first stage boot loader expects u-boot running at this address. */
16 /* The first stage boot loader takes care of low level initialization. */
17 #define CONFIG_SKIP_LOWLEVEL_INIT
19 /* Set our official architecture number. */
20 #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
24 /* ARM asynchronous clock */
25 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
26 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
28 /* 32kB internal SRAM */
29 #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
30 #define CONFIG_SRAM_SIZE (32 << 10)
31 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
32 GENERATED_GBL_DATA_SIZE)
34 /* 128MB SDRAM in 1 bank */
35 #define CONFIG_SYS_SDRAM_BASE 0x20000000
36 #define CONFIG_SYS_SDRAM_SIZE (128 << 20)
37 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
38 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
40 /* 512kB on-chip NOR flash */
41 # define CONFIG_SYS_MAX_FLASH_BANKS 1
42 # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
43 # define CONFIG_AT91_EFLASH
44 # define CONFIG_SYS_MAX_FLASH_SECT 32
45 # define CONFIG_EFLASH_PROTSECTORS 1
48 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
51 #ifdef CONFIG_CMD_NAND
52 #define CONFIG_SYS_MAX_NAND_DEVICE 1
53 #define CONFIG_SYS_NAND_BASE 0x40000000
54 #define CONFIG_SYS_NAND_DBW_8
56 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
58 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
59 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
63 #ifdef CONFIG_CMD_JFFS2
64 #define CONFIG_JFFS2_NAND
68 #define CONFIG_NET_RETRY_COUNT 20
71 #define CONFIG_PHY_ID 0
72 #define CONFIG_MACB_SEARCH_PHY
76 #define CONFIG_GENERIC_ATMEL_MCI
77 #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
82 #define CONFIG_USB_ATMEL
83 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
84 #define CONFIG_USB_OHCI_NEW
85 #define CONFIG_SYS_USB_OHCI_CPU_INIT
86 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
87 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
88 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
92 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
93 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
97 #define CONFIG_SYS_MAX_I2C_BUS 1
99 #define I2C_SOFT_DECLARATIONS
101 #define GPIO_I2C_SCL AT91_PIO_PORTA, 24
102 #define GPIO_I2C_SDA AT91_PIO_PORTA, 23
105 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
106 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
107 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
108 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
109 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
112 #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
113 #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
114 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
115 #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
116 #define I2C_DELAY udelay(100)
117 #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
119 /* DHCP/BOOTP options */
120 #ifdef CONFIG_CMD_DHCP
121 #define CONFIG_BOOTP_BOOTFILESIZE
122 #define CONFIG_SYS_AUTOLOAD "n"
128 #define CONFIG_CMDLINE_TAG
129 #define CONFIG_SETUP_MEMORY_TAGS
130 #define CONFIG_INITRD_TAG
131 #define CONFIG_BOOTCOMMAND "sf probe 0:0; " \
132 "sf read 0x22000000 0xc6000 0x294000; " \
135 /* Misc. u-boot settings */