1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * egnite GmbH <info@egnite.de>
6 * Configuation settings for Ethernut 5 with AT91SAM9XE.
12 #include <asm/hardware.h>
14 /* The first stage boot loader expects u-boot running at this address. */
16 /* The first stage boot loader takes care of low level initialization. */
20 /* ARM asynchronous clock */
21 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
22 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
24 /* 32kB internal SRAM */
25 #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
26 #define CONFIG_SRAM_SIZE (32 << 10)
27 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
28 GENERATED_GBL_DATA_SIZE)
30 /* 128MB SDRAM in 1 bank */
31 #define CONFIG_SYS_SDRAM_BASE 0x20000000
32 #define CONFIG_SYS_SDRAM_SIZE (128 << 20)
34 /* 512kB on-chip NOR flash */
35 # define CONFIG_SYS_MAX_FLASH_BANKS 1
36 # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
37 # define CONFIG_AT91_EFLASH
38 # define CONFIG_SYS_MAX_FLASH_SECT 32
39 # define CONFIG_EFLASH_PROTSECTORS 1
42 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
45 #ifdef CONFIG_CMD_NAND
46 #define CONFIG_SYS_MAX_NAND_DEVICE 1
47 #define CONFIG_SYS_NAND_BASE 0x40000000
48 #define CONFIG_SYS_NAND_DBW_8
50 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
52 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
53 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
57 #ifdef CONFIG_CMD_JFFS2
58 #define CONFIG_JFFS2_NAND
62 #define CONFIG_NET_RETRY_COUNT 20
65 #define CONFIG_PHY_ID 0
66 #define CONFIG_MACB_SEARCH_PHY
70 #define CONFIG_GENERIC_ATMEL_MCI
71 #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
76 #define CONFIG_USB_ATMEL
77 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
78 #define CONFIG_USB_OHCI_NEW
79 #define CONFIG_SYS_USB_OHCI_CPU_INIT
80 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
81 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
82 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
86 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
87 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
91 #define CONFIG_SYS_MAX_I2C_BUS 1
93 #define I2C_SOFT_DECLARATIONS
95 #define GPIO_I2C_SCL AT91_PIO_PORTA, 24
96 #define GPIO_I2C_SDA AT91_PIO_PORTA, 23
99 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
100 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
101 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
102 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
103 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
106 #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
107 #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
108 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
109 #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
110 #define I2C_DELAY udelay(100)
111 #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
113 /* DHCP/BOOTP options */
114 #ifdef CONFIG_CMD_DHCP
115 #define CONFIG_BOOTP_BOOTFILESIZE
116 #define CONFIG_SYS_AUTOLOAD "n"
122 #define CONFIG_BOOTCOMMAND "sf probe 0:0; " \
123 "sf read 0x22000000 0xc6000 0x294000; " \
126 /* Misc. u-boot settings */