3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
8 * Based on davinci_dvevm.h. Original Copyrights follow:
10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
12 * SPDX-License-Identifier: GPL-2.0+
21 #define CONFIG_DRIVER_TI_EMAC
22 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7
23 #define CONFIG_USE_NAND
28 #define CONFIG_ARM926EJS /* arm926ejs CPU core */
29 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
30 #define CONFIG_SOC_DA850 /* TI DA850 SoC */
31 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
32 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
33 #define CONFIG_SYS_OSCIN_FREQ 24000000
34 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
35 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
36 #define CONFIG_SYS_HZ 1000
37 #define CONFIG_DA850_LOWLEVEL
38 #define CONFIG_ARCH_CPU_INIT
39 #define CONFIG_SYS_DA850_PLL_INIT
40 #define CONFIG_SYS_DA850_DDR_INIT
41 #define CONFIG_DA8XX_GPIO
42 #define CONFIG_HOSTNAME enbw_cmc
44 #define MACH_TYPE_ENBW_CMC 3585
45 #define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
50 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
51 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
52 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
53 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
55 /* memtest start addr */
56 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
58 /* memtest will be run on 16MB */
59 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
61 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
66 #define CONFIG_SYS_NS16550
67 #define CONFIG_SYS_NS16550_SERIAL
68 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
69 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
70 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
71 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
72 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
77 #define CONFIG_HARD_I2C
78 #define CONFIG_DRIVER_DAVINCI_I2C
79 #define CONFIG_SYS_I2C_SPEED 80000
80 #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
81 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
82 #define CONFIG_CMD_I2C
84 #define CONFIG_CMD_DTT
85 #define CONFIG_DTT_LM75
86 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
87 #define CONFIG_SYS_DTT_MAX_TEMP 70
88 #define CONFIG_SYS_DTT_LOW_TEMP -30
89 #define CONFIG_SYS_DTT_HYSTERESIS 3
94 #define CONFIG_DAVINCI_SPI
95 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
96 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
97 #define CONFIG_CMD_SPI
100 * Flash & Environment
102 #ifdef CONFIG_USE_NAND
103 #define CONFIG_NAND_DAVINCI
104 #define CONFIG_SYS_NAND_USE_FLASH_BBT
105 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
106 #define CONFIG_SYS_NAND_PAGE_2K
107 #define CONFIG_SYS_NAND_CS 3
108 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
109 #define CONFIG_SYS_NAND_MASK_CLE 0x10
110 #define CONFIG_SYS_NAND_MASK_ALE 0x8
111 #undef CONFIG_SYS_NAND_HW_ECC
112 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
114 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1"
115 #define MTDPARTS_DEFAULT \
129 #define CONFIG_CMD_MTDPARTS
134 * Network & Ethernet Configuration
136 #ifdef CONFIG_DRIVER_TI_EMAC
138 #define CONFIG_BOOTP_DNS
139 #define CONFIG_BOOTP_DNS2
140 #define CONFIG_BOOTP_SEND_HOSTNAME
141 #define CONFIG_NET_RETRY_COUNT 10
145 * Flash configuration
147 #define CONFIG_SYS_FLASH_CFI
148 #define CONFIG_FLASH_CFI_DRIVER
149 #define CONFIG_FLASH_CFI_MTD
150 #define CONFIG_SYS_FLASH_BASE 0x60000000
151 #define CONFIG_SYS_FLASH_SIZE 0x01000000
152 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
153 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
154 #define CONFIG_SYS_MAX_FLASH_SECT 128
155 #define CONFIG_FLASH_16BIT /* Flash is 16-bit */
157 #define CONFIG_CMD_FLASH
159 #define CONFIG_ENV_IS_IN_FLASH
160 #define CONFIG_SYS_MONITOR_LEN 0x80000
161 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
162 CONFIG_SYS_MONITOR_LEN)
163 #define CONFIG_ENV_SECT_SIZE (64 << 10)
164 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
165 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
166 CONFIG_ENV_SECT_SIZE)
167 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
168 #undef CONFIG_ENV_IS_IN_NAND
169 #define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
170 CONFIG_ENV_SECT_SIZE)
172 #define CONFIG_EXTRA_ENV_SETTINGS \
173 "u-boot_addr_r=c0000000\0" \
174 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
175 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
176 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
177 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
178 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
180 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
182 "rootpath=/opt/eldk-arm/arm\0" \
183 "nfsargs=setenv bootargs root=/dev/nfs rw " \
184 "nfsroot=${serverip}:${rootpath}\0" \
185 "ramargs=setenv bootargs root=/dev/ram rw\0" \
186 "addip=setenv bootargs ${bootargs} " \
187 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
188 ":${hostname}:${netdev}:off panic=1\0" \
189 "kernel_addr_r=c0700000\0" \
190 "fdt_addr_r=c0600000\0" \
191 "ramdisk_addr_r=c0b00000\0" \
192 "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \
193 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
194 "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
195 "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \
196 "nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \
197 "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \
198 "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \
199 "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
200 "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \
201 "addcon=setenv bootargs ${bootargs} console=ttyS2," \
203 "net_nfs=run load_fdt load_kernel; " \
204 "run nfsargs addip addcon addmtd addmisc;" \
205 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
206 "nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\
207 "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
208 "bootcmd=run net_nfs\0" \
210 "key_cmd_0=echo key: 0\0" \
211 "key_cmd_1=echo key: 1\0" \
212 "key_cmd_2=echo key: 2\0" \
213 "key_cmd_3=echo key: 3\0" \
218 "magic_keys=0123\0" \
219 "hwconfig=switch:lan=on,pwl=off,config=0x60100000\0" \
220 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
221 "addmisc=setenv bootargs ${bootargs}\0" \
222 "mtdids=" MTDIDS_DEFAULT "\0" \
223 "mtdparts=" MTDPARTS_DEFAULT "\0" \
228 * U-Boot general configuration
230 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
231 #define CONFIG_SYS_PROMPT "=> " /* Command Prompt */
232 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
233 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
234 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
235 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
236 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
237 #define CONFIG_VERSION_VARIABLE
238 #define CONFIG_AUTO_COMPLETE
239 #define CONFIG_SYS_HUSH_PARSER
240 #define CONFIG_CMDLINE_EDITING
241 #define CONFIG_SYS_LONGHELP
242 #define CONFIG_CRC32_VERIFY
243 #define CONFIG_MX_CYCLIC
244 #define CONFIG_BOOTDELAY 3
245 #define CONFIG_HWCONFIG
246 #define CONFIG_SHOW_BOOT_PROGRESS
247 #define CONFIG_BOARD_LATE_INIT
252 #include <config_cmd_default.h>
253 #define CONFIG_CMD_ENV
254 #define CONFIG_CMD_ASKENV
255 #define CONFIG_CMD_DHCP
256 #define CONFIG_CMD_DIAG
257 #define CONFIG_CMD_MII
258 #define CONFIG_CMD_PING
259 #define CONFIG_CMD_SAVES
260 #define CONFIG_CMD_MEMORY
261 #define CONFIG_CMD_CACHE
263 #ifdef CONFIG_CMD_BDI
264 #define CONFIG_CLOCKS
267 #ifndef CONFIG_DRIVER_TI_EMAC
268 #undef CONFIG_CMD_NET
269 #undef CONFIG_CMD_DHCP
270 #undef CONFIG_CMD_MII
271 #undef CONFIG_CMD_PING
274 #ifdef CONFIG_USE_NAND
275 #undef CONFIG_CMD_IMLS
276 #define CONFIG_CMD_NAND
278 #define CONFIG_CMD_MTDPARTS
279 #define CONFIG_MTD_DEVICE
280 #define CONFIG_MTD_PARTITIONS
282 #define CONFIG_RBTREE
283 #define CONFIG_CMD_UBI
284 #define CONFIG_CMD_UBIFS
287 #if !defined(CONFIG_USE_NAND) && \
288 !defined(CONFIG_USE_NOR) && \
289 !defined(CONFIG_USE_SPIFLASH)
290 #define CONFIG_ENV_IS_NOWHERE
291 #define CONFIG_SYS_NO_FLASH
292 #define CONFIG_ENV_SIZE (16 << 10)
293 #undef CONFIG_CMD_IMLS
294 #undef CONFIG_CMD_ENV
297 #define CONFIG_SYS_TEXT_BASE 0x60000000
298 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
299 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
300 #define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
302 #define CONFIG_VERSION_VARIABLE
303 #define CONFIG_ENV_OVERWRITE
305 #define CONFIG_PREBOOT "echo;" \
306 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
308 #define CONFIG_MISC_INIT_R
310 #define CONFIG_CMC_RESET_PIN 0x04000000
311 #define CONFIG_CMC_RESET_TIMEOUT 3
313 #define CONFIG_HW_WATCHDOG
314 #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
315 #define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000
316 #define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
318 #define CONFIG_CMD_DATE
319 #define CONFIG_RTC_DAVINCI
323 #define CONFIG_GENERIC_MMC
324 #define CONFIG_DAVINCI_MMC
325 #define CONFIG_MMC_MBLOCK
326 #define CONFIG_DOS_PARTITION
327 #define CONFIG_CMD_FAT
328 #define CONFIG_CMD_MMC
331 #define CONFIG_ENBW_CMC_BOARD_TYPE 57
332 #define CONFIG_ENBW_CMC_HW_ID_BIT0 39
333 #define CONFIG_ENBW_CMC_HW_ID_BIT1 38
334 #define CONFIG_ENBW_CMC_HW_ID_BIT2 35
337 #define CONFIG_OF_LIBFDT
341 #define CONFIG_SYS_DV_CLKMODE 0
342 #define CONFIG_SYS_DA850_PLL0_POSTDIV 0
343 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
344 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
345 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 /* 150MHz */
346 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
347 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
348 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
349 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
351 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1
352 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
353 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
354 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
356 #define CONFIG_SYS_DA850_PLL0_PLLM 18 /* PLL0 -> 456 MHz */
357 #define CONFIG_SYS_DA850_PLL1_PLLM 24 /* PLL1 -> 300 MHz */
360 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
361 DV_DDR_PHY_EXT_STRBEN | \
362 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
364 #define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
365 (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
366 (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
367 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
368 (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \
369 (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
370 (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \
371 (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
372 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
373 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
374 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
376 #define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
379 * freq = 150MHz -> t = 7ns
381 #define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
382 (0x0d << DV_DDR_SDTMR1_RFC_SHIFT) | \
383 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
384 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
385 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
386 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
387 (7 << DV_DDR_SDTMR1_RC_SHIFT) | \
388 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
389 (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \
390 ((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT))
393 * freq = 150MHz -> t=7ns
395 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
396 (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
397 (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
398 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
399 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
400 (15 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
401 (27 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
402 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
403 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
405 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000407
406 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
407 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
408 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
409 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
410 DAVINCI_SYSCFG_SUSPSRC_EMAC |\
411 DAVINCI_SYSCFG_SUSPSRC_I2C)
413 #define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \
414 DAVINCI_ABCR_WSTROBE(6) | \
415 DAVINCI_ABCR_WHOLD(1) | \
416 DAVINCI_ABCR_RSETUP(2) | \
417 DAVINCI_ABCR_RSTROBE(6) | \
418 DAVINCI_ABCR_RHOLD(1) | \
419 DAVINCI_ABCR_ASIZE_16BIT)
421 #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
422 DAVINCI_ABCR_WSTROBE(2) | \
423 DAVINCI_ABCR_WHOLD(1) | \
424 DAVINCI_ABCR_RSETUP(1) | \
425 DAVINCI_ABCR_RSTROBE(6) | \
426 DAVINCI_ABCR_RHOLD(1) | \
427 DAVINCI_ABCR_ASIZE_8BIT)
430 * NOR Bootconfiguration word:
432 * EMIFA access mode: 16 Bit
434 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
436 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
437 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
438 #define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE
439 #define CONFIG_LOGBUFFER
440 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
442 #define CONFIG_BOOTCOUNT_LIMIT
443 #define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE
444 #define CONFIG_SYS_BOOTCOUNT_BE
446 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000
447 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000
448 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000
449 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
450 #endif /* __CONFIG_H */