2 * Copyright (C) 2014 Eukréa Electromatique
3 * Author: Eric Bénard <eric@eukrea.com>
5 * Configuration settings for the Embest RIoTboard
7 * based on mx6*sabre*.h which are :
8 * Copyright (C) 2012 Freescale Semiconductor, Inc.
10 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef __RIOTBOARD_CONFIG_H
14 #define __RIOTBOARD_CONFIG_H
16 #include "mx6_common.h"
18 #define CONFIG_MXC_UART_BASE UART2_BASE
19 #define CONFIG_CONSOLE_DEV "ttymxc1"
20 #define CONFIG_MMCROOT "/dev/mmcblk1p2"
22 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
24 #define CONFIG_CMDLINE_TAG
25 #define CONFIG_SETUP_MEMORY_TAGS
26 #define CONFIG_INITRD_TAG
27 #define CONFIG_REVISION_TAG
28 #define CONFIG_IMX6_THERMAL
30 /* Size of malloc() pool */
31 #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
33 #define CONFIG_BOARD_EARLY_INIT_F
34 #define CONFIG_BOARD_LATE_INIT
35 #define CONFIG_MXC_GPIO
37 #define CONFIG_MXC_UART
39 #define CONFIG_CMD_FUSE
40 #ifdef CONFIG_CMD_FUSE
41 #define CONFIG_MXC_OCOTP
45 #define CONFIG_CMD_I2C
46 #define CONFIG_SYS_I2C
47 #define CONFIG_SYS_I2C_MXC
48 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
49 #define CONFIG_SYS_I2C_SPEED 100000
52 #define CONFIG_CMD_USB
53 #define CONFIG_USB_EHCI
54 #define CONFIG_USB_EHCI_MX6
55 #define CONFIG_USB_STORAGE
56 #define CONFIG_USB_HOST_ETHER
57 #define CONFIG_USB_ETHER_ASIX
58 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
59 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
60 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
61 #define CONFIG_MXC_USB_FLAGS 0
64 #define CONFIG_FSL_ESDHC
65 #define CONFIG_FSL_USDHC
66 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
69 #define CONFIG_CMD_MMC
70 #define CONFIG_GENERIC_MMC
71 #define CONFIG_BOUNCE_BUFFER
73 #define CONFIG_FEC_MXC
75 #define IMX_FEC_BASE ENET_BASE_ADDR
76 #define CONFIG_FEC_XCV_TYPE RGMII
77 #define CONFIG_ETHPRIME "FEC"
78 #define CONFIG_FEC_MXC_PHYADDR 4
81 #define CONFIG_PHY_ATHEROS
85 #define CONFIG_SPI_FLASH
86 #define CONFIG_SPI_FLASH_SST
87 #define CONFIG_MXC_SPI
88 #define CONFIG_SF_DEFAULT_BUS 0
89 #define CONFIG_SF_DEFAULT_CS 0
90 #define CONFIG_SF_DEFAULT_SPEED 20000000
91 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
94 /* allow to overwrite serial and ethaddr */
95 #define CONFIG_ENV_OVERWRITE
96 #define CONFIG_CONS_INDEX 1
97 #define CONFIG_BAUDRATE 115200
99 /* Command definition */
100 #undef CONFIG_CMD_FPGA
102 #define CONFIG_CMD_BMODE
103 #define CONFIG_CMD_SETEXPR
105 #define CONFIG_LOADADDR 0x12000000
106 #define CONFIG_SYS_TEXT_BASE 0x17800000
108 #define CONFIG_ARP_TIMEOUT 200UL
110 /* Miscellaneous configurable options */
111 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
112 #define CONFIG_SYS_CBSIZE 256
114 /* Print Buffer Size */
115 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
116 #define CONFIG_SYS_MAXARGS 16
117 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
119 #define CONFIG_SYS_MEMTEST_START 0x10000000
120 #define CONFIG_SYS_MEMTEST_END 0x10010000
121 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
123 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
125 #define CONFIG_STACKSIZE (128 * 1024)
127 /* Physical Memory Map */
128 #define CONFIG_NR_DRAM_BANKS 1
129 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
131 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
132 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
133 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
135 #define CONFIG_SYS_INIT_SP_OFFSET \
136 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
137 #define CONFIG_SYS_INIT_SP_ADDR \
138 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
140 /* Environment organization */
141 #define CONFIG_ENV_SIZE (8 * 1024)
143 #if defined(CONFIG_ENV_IS_IN_MMC)
145 #define CONFIG_FDTFILE "imx6dl-riotboard.dtb"
146 #define CONFIG_SYS_FSL_USDHC_NUM 3
147 #define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */
148 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
149 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
150 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
152 #define CONFIG_FDTFILE "imx6q-marsboard.dtb"
153 #define CONFIG_SYS_FSL_USDHC_NUM 2
154 #define CONFIG_ENV_OFFSET (768 * 1024)
155 #define CONFIG_ENV_SECT_SIZE (8 * 1024)
156 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
157 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
158 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
159 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
162 #ifndef CONFIG_SYS_DCACHE_OFF
163 #define CONFIG_CMD_CACHE
168 #define CONFIG_VIDEO_IPUV3
169 #define CONFIG_CFB_CONSOLE
170 #define CONFIG_VGA_AS_SINGLE_DEVICE
171 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
172 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
173 #define CONFIG_VIDEO_BMP_RLE8
174 #define CONFIG_SPLASH_SCREEN
175 #define CONFIG_SPLASH_SCREEN_ALIGN
176 #define CONFIG_BMP_16BPP
177 #define CONFIG_VIDEO_LOGO
178 #define CONFIG_VIDEO_BMP_LOGO
179 #define CONFIG_IPUV3_CLK 260000000
180 #define CONFIG_IMX_HDMI
181 #define CONFIG_IMX_VIDEO_SKIP
183 #include <config_distro_defaults.h>
185 /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
186 * 1M script, 1M pxe and the ramdisk at the end */
187 #define MEM_LAYOUT_ENV_SETTINGS \
188 "bootm_size=0x10000000\0" \
189 "kernel_addr_r=0x12000000\0" \
190 "fdt_addr_r=0x13000000\0" \
191 "scriptaddr=0x13100000\0" \
192 "pxefile_addr_r=0x13200000\0" \
193 "ramdisk_addr_r=0x13300000\0"
195 #define BOOT_TARGET_DEVICES(func) \
203 #include <config_distro_bootcmd.h>
205 #define CONSOLE_STDIN_SETTINGS \
208 #define CONSOLE_STDOUT_SETTINGS \
212 #define CONSOLE_ENV_SETTINGS \
213 CONSOLE_STDIN_SETTINGS \
214 CONSOLE_STDOUT_SETTINGS
216 #define CONFIG_EXTRA_ENV_SETTINGS \
217 CONSOLE_ENV_SETTINGS \
218 MEM_LAYOUT_ENV_SETTINGS \
219 "fdtfile=" CONFIG_FDTFILE "\0" \
222 #endif /* __RIOTBOARD_CONFIG_H */