1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014 Eukréa Electromatique
4 * Author: Eric Bénard <eric@eukrea.com>
6 * Configuration settings for the Embest RIoTboard
8 * based on mx6*sabre*.h which are :
9 * Copyright (C) 2012 Freescale Semiconductor, Inc.
12 #ifndef __RIOTBOARD_CONFIG_H
13 #define __RIOTBOARD_CONFIG_H
15 #define CONFIG_MXC_UART_BASE UART2_BASE
16 #define CONSOLE_DEV "ttymxc1"
18 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
20 #define CONFIG_IMX_THERMAL
22 /* Size of malloc() pool */
23 #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
25 #define CONFIG_MXC_UART
28 #define CONFIG_SYS_I2C
29 #define CONFIG_SYS_I2C_MXC
30 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
31 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
32 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
33 #define CONFIG_SYS_I2C_SPEED 100000
36 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
37 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
38 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
39 #define CONFIG_MXC_USB_FLAGS 0
42 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
44 #define CONFIG_FEC_MXC
45 #define IMX_FEC_BASE ENET_BASE_ADDR
46 #define CONFIG_FEC_XCV_TYPE RGMII
47 #define CONFIG_ETHPRIME "FEC"
48 #define CONFIG_FEC_MXC_PHYADDR 4
50 #define CONFIG_PHY_ATHEROS
52 #define CONFIG_ARP_TIMEOUT 200UL
54 #define CONFIG_SYS_MEMTEST_START 0x10000000
55 #define CONFIG_SYS_MEMTEST_END 0x10010000
56 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
58 /* Physical Memory Map */
59 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
61 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
62 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
63 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
65 #define CONFIG_SYS_INIT_SP_OFFSET \
66 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
67 #define CONFIG_SYS_INIT_SP_ADDR \
68 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
70 /* Environment organization */
71 #define CONFIG_ENV_SIZE (8 * 1024)
73 #if defined(CONFIG_ENV_IS_IN_MMC)
75 #define CONFIG_FDTFILE "imx6dl-riotboard.dtb"
76 #define CONFIG_SYS_FSL_USDHC_NUM 3
77 #define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */
78 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
79 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
81 #define CONFIG_FDTFILE "imx6q-marsboard.dtb"
82 #define CONFIG_SYS_FSL_USDHC_NUM 2
83 #define CONFIG_ENV_OFFSET (768 * 1024)
84 #define CONFIG_ENV_SECT_SIZE (8 * 1024)
88 #define CONFIG_VIDEO_BMP_RLE8
89 #define CONFIG_SPLASH_SCREEN
90 #define CONFIG_SPLASH_SCREEN_ALIGN
91 #define CONFIG_BMP_16BPP
92 #define CONFIG_VIDEO_LOGO
93 #define CONFIG_VIDEO_BMP_LOGO
94 #define CONFIG_IMX_HDMI
95 #define CONFIG_IMX_VIDEO_SKIP
97 #include "mx6_common.h"
100 #include "imx6_spl.h"
102 #define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000
103 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
104 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6dl-riotboard.dtb"
106 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* offset 69KB */
107 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* offset 69KB */
108 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* offset 69KB */
112 /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
113 * 1M script, 1M pxe and the ramdisk at the end */
114 #define MEM_LAYOUT_ENV_SETTINGS \
115 "bootm_size=0x10000000\0" \
116 "kernel_addr_r=0x12000000\0" \
117 "fdt_addr_r=0x13000000\0" \
118 "scriptaddr=0x13100000\0" \
119 "pxefile_addr_r=0x13200000\0" \
120 "ramdisk_addr_r=0x13300000\0"
122 #define BOOT_TARGET_DEVICES(func) \
130 #include <config_distro_bootcmd.h>
132 #define CONSOLE_STDIN_SETTINGS \
135 #define CONSOLE_STDOUT_SETTINGS \
139 #define CONSOLE_ENV_SETTINGS \
140 CONSOLE_STDIN_SETTINGS \
141 CONSOLE_STDOUT_SETTINGS
143 #define CONFIG_EXTRA_ENV_SETTINGS \
144 CONSOLE_ENV_SETTINGS \
145 MEM_LAYOUT_ENV_SETTINGS \
146 "fdtfile=" CONFIG_FDTFILE "\0" \
147 "finduuid=part uuid mmc 0:1 uuid\0" \
150 #endif /* __RIOTBOARD_CONFIG_H */