1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014 Eukréa Electromatique
4 * Author: Eric Bénard <eric@eukrea.com>
6 * Configuration settings for the Embest RIoTboard
8 * based on mx6*sabre*.h which are :
9 * Copyright (C) 2012 Freescale Semiconductor, Inc.
12 #ifndef __RIOTBOARD_CONFIG_H
13 #define __RIOTBOARD_CONFIG_H
15 #define CONFIG_MXC_UART_BASE UART2_BASE
16 #define CONSOLE_DEV "ttymxc1"
18 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
20 #define CONFIG_IMX_THERMAL
22 /* Size of malloc() pool */
23 #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
25 #define CONFIG_MXC_UART
28 #define CONFIG_SYS_I2C
29 #define CONFIG_SYS_I2C_MXC
30 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
31 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
32 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
33 #define CONFIG_SYS_I2C_SPEED 100000
36 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
37 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
38 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
39 #define CONFIG_MXC_USB_FLAGS 0
42 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
44 #define CONFIG_FEC_MXC
46 #define IMX_FEC_BASE ENET_BASE_ADDR
47 #define CONFIG_FEC_XCV_TYPE RGMII
48 #define CONFIG_ETHPRIME "FEC"
49 #define CONFIG_FEC_MXC_PHYADDR 4
51 #define CONFIG_PHY_ATHEROS
54 #define CONFIG_SF_DEFAULT_BUS 0
55 #define CONFIG_SF_DEFAULT_CS 0
56 #define CONFIG_SF_DEFAULT_SPEED 20000000
57 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
60 #define CONFIG_ARP_TIMEOUT 200UL
62 #define CONFIG_SYS_MEMTEST_START 0x10000000
63 #define CONFIG_SYS_MEMTEST_END 0x10010000
64 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
66 /* Physical Memory Map */
67 #define CONFIG_NR_DRAM_BANKS 1
68 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
70 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
71 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
72 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
74 #define CONFIG_SYS_INIT_SP_OFFSET \
75 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
76 #define CONFIG_SYS_INIT_SP_ADDR \
77 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
79 /* Environment organization */
80 #define CONFIG_ENV_SIZE (8 * 1024)
82 #if defined(CONFIG_ENV_IS_IN_MMC)
84 #define CONFIG_FDTFILE "imx6dl-riotboard.dtb"
85 #define CONFIG_SYS_FSL_USDHC_NUM 3
86 #define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */
87 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
88 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
89 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
91 #define CONFIG_FDTFILE "imx6q-marsboard.dtb"
92 #define CONFIG_SYS_FSL_USDHC_NUM 2
93 #define CONFIG_ENV_OFFSET (768 * 1024)
94 #define CONFIG_ENV_SECT_SIZE (8 * 1024)
95 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
96 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
97 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
98 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
102 #define CONFIG_VIDEO_IPUV3
103 #define CONFIG_VIDEO_BMP_RLE8
104 #define CONFIG_SPLASH_SCREEN
105 #define CONFIG_SPLASH_SCREEN_ALIGN
106 #define CONFIG_BMP_16BPP
107 #define CONFIG_VIDEO_LOGO
108 #define CONFIG_VIDEO_BMP_LOGO
109 #define CONFIG_IMX_HDMI
110 #define CONFIG_IMX_VIDEO_SKIP
112 #include "mx6_common.h"
114 /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
115 * 1M script, 1M pxe and the ramdisk at the end */
116 #define MEM_LAYOUT_ENV_SETTINGS \
117 "bootm_size=0x10000000\0" \
118 "kernel_addr_r=0x12000000\0" \
119 "fdt_addr_r=0x13000000\0" \
120 "scriptaddr=0x13100000\0" \
121 "pxefile_addr_r=0x13200000\0" \
122 "ramdisk_addr_r=0x13300000\0"
124 #define BOOT_TARGET_DEVICES(func) \
132 #include <config_distro_bootcmd.h>
134 #define CONSOLE_STDIN_SETTINGS \
137 #define CONSOLE_STDOUT_SETTINGS \
141 #define CONSOLE_ENV_SETTINGS \
142 CONSOLE_STDIN_SETTINGS \
143 CONSOLE_STDOUT_SETTINGS
145 #define CONFIG_EXTRA_ENV_SETTINGS \
146 CONSOLE_ENV_SETTINGS \
147 MEM_LAYOUT_ENV_SETTINGS \
148 "fdtfile=" CONFIG_FDTFILE "\0" \
149 "finduuid=part uuid mmc 0:1 uuid\0" \
152 #endif /* __RIOTBOARD_CONFIG_H */