2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
4 * Based on original Kirkwood support which is
6 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 #ifndef _CONFIG_EDMINIV2_H
13 #define _CONFIG_EDMINIV2_H
19 #define CONFIG_SPL_FRAMEWORK
20 #define CONFIG_SPL_SERIAL_SUPPORT
21 #define CONFIG_SPL_NOR_SUPPORT
22 #define CONFIG_SPL_TEXT_BASE 0xffff0000
23 #define CONFIG_SPL_MAX_SIZE 0x0000fff0
24 #define CONFIG_SPL_STACK 0x00020000
25 #define CONFIG_SPL_BSS_START_ADDR 0x00020000
26 #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
27 #define CONFIG_SYS_SPL_MALLOC_START 0x00040000
28 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
29 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds"
30 #define CONFIG_SPL_BOARD_INIT
31 #define CONFIG_SYS_UBOOT_BASE 0xfff90000
32 #define CONFIG_SYS_UBOOT_START 0x00800000
33 #define CONFIG_SYS_TEXT_BASE 0x00800000
36 * Version number information
39 #define CONFIG_IDENT_STRING " EDMiniV2"
42 * High Level Configuration Options (easy to change)
45 #define CONFIG_MARVELL 1
46 #define CONFIG_FEROCEON 1 /* CPU Core subversion */
47 #define CONFIG_88F5182 1 /* SOC Name */
48 #define CONFIG_MACH_EDMINIV2 1 /* Machine type */
50 #include <asm/arch/orion5x.h>
56 * Board-specific values for Orion5x MPP low level init:
57 * - MPPs 12 to 15 are SATA LEDs (mode 5)
58 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
59 * MPP16 to MPP19, mode 0 for others
62 #define ORION5X_MPP0_7 0x00000003
63 #define ORION5X_MPP8_15 0x55550000
64 #define ORION5X_MPP16_23 0x00005555
67 * Board-specific values for Orion5x GPIO low level init:
68 * - GPIO3 is input (RTC interrupt)
69 * - GPIO16 is Power LED control (0 = on, 1 = off)
70 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
71 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
72 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
73 * - GPIO22 is SATA disk power status ()
74 * - GPIO23 is supply status for SATA disk ()
75 * - GPIO24 is supply control for board (write 1 to power off)
76 * Last GPIO is 25, further bits are supposed to be 0.
77 * Enable mask has ones for INPUT, 0 for OUTPUT.
78 * Default is LED ON, board ON :)
81 #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca
82 #define ORION5X_GPIO_OUT_VALUE 0x00000000
83 #define ORION5X_GPIO_IN_POLARITY 0x000000d0
86 * NS16550 Configuration
89 #define CONFIG_SYS_NS16550_SERIAL
90 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
91 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
92 #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
95 * Serial Port configuration
96 * The following definitions let you select what serial you want to use
97 * for your console driver.
100 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */
101 #define CONFIG_BAUDRATE 115200
102 #define CONFIG_SYS_BAUDRATE_TABLE \
103 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
106 * FLASH configuration
109 #define CONFIG_SYS_FLASH_CFI
110 #define CONFIG_FLASH_CFI_DRIVER
111 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
112 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
113 #define CONFIG_SYS_FLASH_BASE 0xfff80000
118 * For booting Linux, the board info and command line data
119 * have to be in the first 8 MB of memory, since this is
120 * the maximum mapped by the Linux kernel during initialization.
122 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
123 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
124 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
126 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
127 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
128 +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
130 * Commands configuration
132 #define CONFIG_CMD_IDE
138 #ifdef CONFIG_CMD_NET
139 #define CONFIG_MVGBE /* Enable Marvell GbE Driver */
140 #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
141 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
142 #define CONFIG_PHY_BASE_ADR 0x8
143 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
144 #define CONFIG_NETCONSOLE /* include NetConsole support */
145 #define CONFIG_MII /* expose smi ove miiphy interface */
146 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
147 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
153 #ifdef CONFIG_CMD_IDE
155 #define CONFIG_IDE_PREINIT
156 #define CONFIG_DOS_PARTITION
157 /* ED Mini V has an IDE-compatible SATA connector for port 1 */
158 #define CONFIG_MVSATA_IDE
159 #define CONFIG_MVSATA_IDE_USE_PORT1
160 /* Needs byte-swapping for ATA data register */
161 #define CONFIG_IDE_SWAP_IO
162 /* Data, registers and alternate blocks are at the same offset */
163 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
164 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
165 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
166 /* Each 8-bit ATA register is aligned to a 4-bytes address */
167 #define CONFIG_SYS_ATA_STRIDE 4
168 /* Controller supports 48-bits LBA addressing */
170 /* A single bus, a single device */
171 #define CONFIG_SYS_IDE_MAXBUS 1
172 #define CONFIG_SYS_IDE_MAXDEVICE 1
173 /* ATA registers base is at SATA controller base */
174 #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
175 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */
176 #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
177 /* end of IDE defines */
181 * Common USB/EHCI configuration
183 #ifdef CONFIG_CMD_USB
184 #define CONFIG_USB_EHCI /* Enable EHCI USB support */
185 #define CONFIG_USB_EHCI_MARVELL
186 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
187 #define CONFIG_DOS_PARTITION
188 #define CONFIG_ISO_PARTITION
189 #define CONFIG_SUPPORT_VFAT
190 #endif /* CONFIG_CMD_USB */
195 #ifdef CONFIG_CMD_I2C
196 #define CONFIG_SYS_I2C
197 #define CONFIG_SYS_I2C_MVTWSI
198 #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE
199 #define CONFIG_SYS_I2C_SLAVE 0x0
200 #define CONFIG_SYS_I2C_SPEED 100000
204 * Environment variables configurations
206 #define CONFIG_ENV_IS_IN_FLASH 1
207 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */
208 #define CONFIG_ENV_SIZE 0x2000
209 #define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
212 * Size of malloc() pool
214 #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */
217 * Other required minimal configurations
219 #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
220 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
221 #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
222 #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
223 #define CONFIG_NR_DRAM_BANKS 1
225 #define CONFIG_SYS_LOAD_ADDR 0x00800000
226 #define CONFIG_SYS_MEMTEST_START 0x00400000
227 #define CONFIG_SYS_MEMTEST_END 0x007fffff
228 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000
229 #define CONFIG_SYS_MAXARGS 16
231 /* Enable command line editing */
232 #define CONFIG_CMDLINE_EDITING
234 /* provide extensive help */
235 #define CONFIG_SYS_LONGHELP
237 /* additions for new relocation code, must be added to all boards */
238 #define CONFIG_SYS_SDRAM_BASE 0
239 #define CONFIG_SYS_INIT_SP_ADDR \
240 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
242 #endif /* _CONFIG_EDMINIV2_H */