2 * (C) Copyright 2008-2009
3 * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
4 * Jens Scharsig <esw@bus-elektronik.de>
6 * Configuation settings for the EB+CPUx9K2 board.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #ifndef _CONFIG_EB_CPUx9K2_H_
28 #define _CONFIG_EB_CPUx9K2_H_
30 /*--------------------------------------------------------------------------*/
32 #define CONFIG_AT91RM9200 /* It's an Atmel AT91RM9200 SoC */
33 #define CONFIG_EB_CPUX9K2 /* on an EP+CPUX9K2 Board */
36 #define CONFIG_VERSION_VARIABLE
37 #define CONFIG_IDENT_STRING " on EB+CPUx9K2"
39 #include <asm/hardware.h> /* needed for port definitions */
41 #define CONFIG_MISC_INIT_R
42 #define CONFIG_BOARD_EARLY_INIT_F
44 #define MACH_TYPE_EB_CPUX9K2 1977
45 #define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2
47 #define CONFIG_SYS_CACHELINE_SIZE 32
48 #define CONFIG_SYS_DCACHE_OFF
50 /*--------------------------------------------------------------------------*/
51 #ifndef CONFIG_RAMBOOT
52 #define CONFIG_SYS_TEXT_BASE 0x00000000
54 #define CONFIG_SKIP_LOWLEVEL_INIT
55 #define CONFIG_SYS_TEXT_BASE 0x21f00000
57 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
59 #define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
60 #define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
61 #define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
63 #define CONFIG_BOOT_RETRY_TIME 30
64 #define CONFIG_CMDLINE_EDITING
66 #define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
67 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
68 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
69 #define CONFIG_SYS_PBSIZE \
70 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
73 * ARM asynchronous clock
76 #define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */
77 #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
78 #define CONFIG_SYS_HZ 1000
79 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
81 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
83 #define CONFIG_CMDLINE_TAG 1
84 #define CONFIG_SETUP_MEMORY_TAGS 1
85 #define CONFIG_INITRD_TAG 1
87 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
89 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
90 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
93 #define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */
94 #define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */
95 #define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */
98 * Size of malloc() pool
101 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 520*1024)
107 #define CONFIG_NR_DRAM_BANKS 1
109 #define CONFIG_SYS_SDRAM_BASE 0x20000000
110 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
111 #define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */
113 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
114 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
115 CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
116 CONFIG_SYS_MALLOC_LEN)
118 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */
119 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
120 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
121 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
122 #define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */
123 #define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
124 #define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
125 #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
126 #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
127 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
128 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
129 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
130 #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
133 * Command line configuration
136 #include <config_cmd_default.h>
138 #define CONFIG_CMD_BMP
139 #define CONFIG_CMD_DATE
140 #define CONFIG_CMD_DHCP
141 #define CONFIG_CMD_I2C
142 #define CONFIG_CMD_JFFS2
143 #define CONFIG_CMD_MII
144 #define CONFIG_CMD_NAND
145 #define CONFIG_CMD_PING
146 #define CONFIG_I2C_CMD_NO_FLAT
147 #define CONFIG_I2C_CMD_TREE
148 #define CONFIG_CMD_USB
149 #define CONFIG_CMD_FAT
151 #define CONFIG_SYS_LONGHELP
157 #define CONFIG_JFFS2_NAND 1
159 #ifndef CONFIG_JFFS2_CMDLINE
160 #define CONFIG_JFFS2_DEV "nand0"
161 #define CONFIG_JFFS2_PART_OFFSET 0
162 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
164 #define MTDIDS_DEFAULT "nor0=0,nand0=1"
165 #define MTDPARTS_DEFAULT "mtdparts=" \
175 #endif /* CONFIG_JFFS2_CMDLINE */
180 #define CONFIG_USB_ATMEL
181 #define CONFIG_USB_OHCI_NEW
182 #define CONFIG_AT91C_PQFP_UHPBUG
183 #define CONFIG_USB_STORAGE
184 #define CONFIG_DOS_PARTITION
185 #define CONFIG_ISO_PARTITION
186 #define CONFIG_EFI_PARTITION
188 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
189 #define CONFIG_SYS_USB_OHCI_CPU_INIT
190 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00300000
191 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
197 #define CONFIG_BAUDRATE 115200
198 #define CONFIG_ATMEL_USART
199 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
200 #define CONFIG_USART_ID 0/* ignored in arm */
206 #define CONFIG_NET_RETRY_COUNT 10
207 #define CONFIG_RESET_PHY_R 1
209 #define CONFIG_DRIVER_AT91EMAC 1
210 #define CONFIG_DRIVER_AT91EMAC_QUIET 1
211 #define CONFIG_SYS_RX_ETH_BUFFER 8
217 #define CONFIG_BOOTP_BOOTFILESIZE
218 #define CONFIG_BOOTP_BOOTPATH
219 #define CONFIG_BOOTP_GATEWAY
220 #define CONFIG_BOOTP_HOSTNAME
226 #define CONFIG_SYS_I2C
227 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
228 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
229 #define CONFIG_SYS_I2C_SOFT_SLAVE 0
231 /* Software I2C driver configuration */
233 #define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */
234 #define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */
236 #define CONFIG_SYS_I2C_INIT_BOARD
238 #define I2C_INIT i2c_init_board();
239 #define I2C_ACTIVE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
240 #define I2C_TRISTATE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
241 #define I2C_READ ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
242 #define I2C_SDA(bit) \
244 writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr); \
246 writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
247 #define I2C_SCL(bit) \
249 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr); \
251 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
253 #define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED)
257 #ifdef CONFIG_CMD_DATE
258 #define CONFIG_RTC_DS1338
259 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
264 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
265 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
267 /* FLASH organization */
270 #define CONFIG_FLASH_SHOW_PROGRESS 45
272 #define CONFIG_FLASH_CFI_DRIVER 1
274 #define PHYS_FLASH_1 0x10000000
275 #define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */
276 #define CONFIG_SYS_FLASH_CFI 1
277 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
279 #define CONFIG_SYS_FLASH_PROTECTION 1
280 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
281 #define CONFIG_SYS_MAX_FLASH_BANKS 1
282 #define CONFIG_SYS_MAX_FLASH_SECT 512
283 #define CONFIG_SYS_FLASH_ERASE_TOUT 6000
284 #define CONFIG_SYS_FLASH_WRITE_TOUT 2000
288 #define CONFIG_SYS_MAX_NAND_DEVICE 1
289 #define CONFIG_SYS_NAND_BASE 0x40000000
290 #define CONFIG_SYS_NAND_DBW_8 1
294 #define CONFIG_STATUS_LED 1
295 #define CONFIG_BOARD_SPECIFIC_LED 1
297 #define STATUS_LED_BOOT 1
298 #define STATUS_LED_ACTIVE 0
300 #define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */
301 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
302 #define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */
303 #define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */
304 #define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */
305 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4)
307 #define CONFIG_VIDEO 1
313 #define CONFIG_VIDEO_VCXK 1
315 #define CONFIG_SPLASH_SCREEN 1
317 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4
318 #define CONFIG_SYS_VCXK_BASE 0x30000000
320 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3)
321 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob
322 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr
324 #define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5)
325 #define CONFIG_SYS_VCXK_ENABLE_PORT piob
326 #define CONFIG_SYS_VCXK_ENABLE_DDR oer
328 #define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2)
329 #define CONFIG_SYS_VCXK_REQUEST_PORT piob
330 #define CONFIG_SYS_VCXK_REQUEST_DDR oer
332 #define CONFIG_SYS_VCXK_INVERT_PIN (1<<4)
333 #define CONFIG_SYS_VCXK_INVERT_PORT piob
334 #define CONFIG_SYS_VCXK_INVERT_DDR oer
336 #define CONFIG_SYS_VCXK_RESET_PIN (1<<6)
337 #define CONFIG_SYS_VCXK_RESET_PORT piob
338 #define CONFIG_SYS_VCXK_RESET_DDR oer
340 #endif /* CONFIG_VIDEO */
344 #define CONFIG_BOOTDELAY 5
346 #define CONFIG_ENV_IS_IN_FLASH 1
347 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
348 #define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
350 #define CONFIG_BAUDRATE 115200
352 #define CONFIG_BOOTCOMMAND "run nfsboot"
354 #define CONFIG_NFSBOOTCOMMAND \
355 "dhcp $(copy_addr) uImage_cpux9k2;" \
356 "run bootargsdefaults;" \
357 "set bootargs $(bootargs) boot=nfs " \
358 ";echo $(bootargs)" \
361 #define CONFIG_EXTRA_ENV_SETTINGS \
362 "displaywidth=256\0" \
363 "displayheight=512\0" \
364 "displaybsteps=1023\0" \
365 "ubootaddr=10000000\0" \
366 "splashimage=10080000\0" \
367 "kerneladdr=100A0000\0" \
368 "kernelsize=00400000\0" \
369 "rootfsaddr=104A0000\0" \
370 "copy_addr=21200000\0" \
371 "rootfssize=00B60000\0" \
372 "bootargsdefaults=set bootargs " \
373 "console=ttyS0,115200 " \
374 "video=vcxk_fb:xres:${displaywidth}," \
375 "yres:${displayheight}," \
376 "bres:${displaybsteps} " \
379 "uboot=\\\"${ver}\\\" " \
381 "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
382 "dhcp $(copy_addr) uImage_cpux9k2;" \
383 "erase $(kerneladdr) +$(kernelsize);" \
384 "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
385 "protect on $(kerneladdr) +$(kernelsize)" \
387 "update_root=protect off $(rootfsaddr) +$(rootfssize);" \
388 "dhcp $(copy_addr) rfs;" \
389 "erase $(rootfsaddr) +$(rootfssize);" \
390 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
392 "update_uboot=protect off 10000000 1005FFFF;" \
393 "dhcp $(copy_addr) u-boot_eb_cpux9k2;" \
394 "erase 10000000 1005FFFF;" \
395 "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
396 "protect on 10000000 1005FFFF;reset\0" \
397 "update_splash=protect off $(splashimage) +20000;" \
398 "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \
399 "erase $(splashimage) +20000;" \
400 "cp.b $(fileaddr) 10080000 $(filesize);" \
401 "protect on $(splashimage) +20000;reset\0" \
402 "emergency=run bootargsdefaults;" \
403 "set bootargs $(bootargs) root=initramfs boot=emergency " \
404 ";bootm $(kerneladdr)\0" \
405 "netemergency=run bootargsdefaults;" \
406 "dhcp $(copy_addr) uImage_cpux9k2;" \
407 "set bootargs $(bootargs) root=initramfs boot=emergency " \
408 ";bootm $(copy_addr)\0" \
409 "norboot=run bootargsdefaults;" \
410 "set bootargs $(bootargs) root=initramfs boot=local " \
411 ";bootm $(kerneladdr)\0" \
412 "nandboot=run bootargsdefaults;" \
413 "set bootargs $(bootargs) root=initramfs boot=nand " \
414 ";bootm $(kerneladdr)\0" \
417 /*--------------------------------------------------------------------------*/