Merge branch 'master' of git://git.denx.de/u-boot-mips
[platform/kernel/u-boot.git] / include / configs / eb_cpux9k2.h
1 /*
2  * (C) Copyright 2008-2009
3  * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
4  * Jens Scharsig <esw@bus-elektronik.de>
5  *
6  * Configuation settings for the EB+CPUx9K2 board.
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #ifndef _CONFIG_EB_CPUx9K2_H_
12 #define _CONFIG_EB_CPUx9K2_H_
13
14 /*--------------------------------------------------------------------------*/
15
16 #define CONFIG_AT91RM9200               /* It's an Atmel AT91RM9200 SoC */
17 #define CONFIG_EB_CPUX9K2               /* on an EP+CPUX9K2 Board       */
18 #define USE_920T_MMU
19
20 #define CONFIG_VERSION_VARIABLE
21 #define CONFIG_IDENT_STRING     " on EB+CPUx9K2"
22
23 #include <asm/hardware.h>       /* needed for port definitions */
24
25 #define CONFIG_MISC_INIT_R
26 #define CONFIG_BOARD_EARLY_INIT_F
27
28 #define MACH_TYPE_EB_CPUX9K2            1977
29 #define CONFIG_MACH_TYPE                MACH_TYPE_EB_CPUX9K2
30
31 #define CONFIG_SYS_CACHELINE_SIZE       32
32 #define CONFIG_SYS_DCACHE_OFF
33
34 /*--------------------------------------------------------------------------*/
35 #ifndef CONFIG_RAMBOOT
36 #define CONFIG_SYS_TEXT_BASE            0x00000000
37 #else
38 #define CONFIG_SKIP_LOWLEVEL_INIT
39 #define CONFIG_SYS_TEXT_BASE            0x21800000
40 #endif
41 #define CONFIG_SYS_LOAD_ADDR            0x21000000  /* default load address */
42 #define CONFIG_STANDALONE_LOAD_ADDR     0x21000000
43
44 #define CONFIG_SYS_BOOT_SIZE            0x00 /* 0 KBytes */
45 #define CONFIG_SYS_U_BOOT_BASE          PHYS_FLASH_1
46 #define CONFIG_SYS_U_BOOT_SIZE          0x60000 /* 384 KBytes */
47
48 #define CONFIG_BOOT_RETRY_TIME          30
49 #define CONFIG_CMDLINE_EDITING
50
51 #define CONFIG_SYS_PROMPT       "U-Boot> "      /* Monitor Command Prompt */
52 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
53 #define CONFIG_SYS_MAXARGS      32              /* max number of command args */
54 #define CONFIG_SYS_PBSIZE       \
55         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
56
57 /*
58  * ARM asynchronous clock
59  */
60
61 #define AT91C_MAIN_CLOCK        179404800       /* from 12.288 MHz * 73 / 5 */
62 #define AT91C_MASTER_CLOCK      (AT91C_MAIN_CLOCK / 3)
63 #define CONFIG_SYS_HZ_CLOCK     (AT91C_MASTER_CLOCK / 2)
64
65 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock */
66
67 #define CONFIG_CMDLINE_TAG              1
68 #define CONFIG_SETUP_MEMORY_TAGS        1
69 #define CONFIG_INITRD_TAG               1
70
71 #define CONFIG_SYS_USE_MAIN_OSCILLATOR  1
72 /* flash */
73 #define CONFIG_SYS_EBI_CFGR_VAL         0x00000000
74 #define CONFIG_SYS_SMC_CSR0_VAL         0x00003284 /* 16bit, 2 TDF, 4 WS */
75
76 /* clocks */
77 #define CONFIG_SYS_PLLAR_VAL            0x20483E05 /* 179.4048 MHz for PCK */
78 #define CONFIG_SYS_PLLBR_VAL            0x104C3E0A /* 47.3088 MHz (for USB) */
79 #define CONFIG_SYS_MCKR_VAL             0x00000202 /* PCK/3 = MCK Clock */
80
81 /*
82  * Size of malloc() pool
83  */
84
85 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
86
87 /*
88  * sdram
89  */
90
91 #define CONFIG_NR_DRAM_BANKS            1
92
93 #define CONFIG_SYS_SDRAM_BASE           0x20000000
94 #define CONFIG_SYS_SDRAM_SIZE           0x04000000  /* 64 megs */
95 #define CONFIG_SYS_INIT_SP_ADDR         0x00204000  /* use internal SRAM */
96
97 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
98 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
99                                         CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
100                                         CONFIG_SYS_MALLOC_LEN)
101
102 #define CONFIG_SYS_PIOC_ASR_VAL         0xFFFF0000 /* PIOC as D16/D31 */
103 #define CONFIG_SYS_PIOC_BSR_VAL         0x00000000
104 #define CONFIG_SYS_PIOC_PDR_VAL         0xFFFF0000
105 #define CONFIG_SYS_EBI_CSA_VAL          0x00000002 /* CS1=SDRAM */
106 #define CONFIG_SYS_SDRC_CR_VAL          0x2188c159 /* set up the SDRAM */
107 #define CONFIG_SYS_SDRAM                0x20000000 /* address of the SDRAM */
108 #define CONFIG_SYS_SDRAM1               0x20000080 /* address of the SDRAM */
109 #define CONFIG_SYS_SDRAM_VAL            0x00000000 /* value written to SDRAM */
110 #define CONFIG_SYS_SDRC_MR_VAL          0x00000002 /* Precharge All */
111 #define CONFIG_SYS_SDRC_MR_VAL1         0x00000004 /* refresh */
112 #define CONFIG_SYS_SDRC_MR_VAL2         0x00000003 /* Load Mode Register */
113 #define CONFIG_SYS_SDRC_MR_VAL3         0x00000000 /* Normal Mode */
114 #define CONFIG_SYS_SDRC_TR_VAL          0x000002E0 /* Write refresh rate */
115
116 /*
117  * Command line configuration
118  */
119
120 #include <config_cmd_default.h>
121
122 #define CONFIG_CMD_BMP
123 #define CONFIG_CMD_DATE
124 #define CONFIG_CMD_DHCP
125 #define CONFIG_CMD_I2C
126 #define CONFIG_CMD_MII
127 #define CONFIG_CMD_NAND
128 #define CONFIG_CMD_PING
129 #define CONFIG_I2C_CMD_TREE
130 #define CONFIG_CMD_USB
131 #define CONFIG_CMD_FAT
132 #define CONFIG_CMD_UBI
133 #define CONFIG_CMD_MTDPARTS
134 #define CONFIG_CMD_UBIFS
135
136 #define CONFIG_SYS_LONGHELP
137
138 /*
139  * MTD defines
140  */
141
142 #define CONFIG_FLASH_CFI_MTD
143 #define CONFIG_MTD_DEVICE
144 #define CONFIG_MTD_PARTITIONS
145 #define CONFIG_RBTREE
146 #define CONFIG_LZO
147
148 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0,nand0=atmel_nand"
149 #define MTDPARTS_DEFAULT        "mtdparts="                             \
150                                         "physmap-flash.0:"              \
151                                                 "512k(U-Boot),"         \
152                                                 "128k(Env),"            \
153                                                 "128k(Splash),"         \
154                                                 "4M(Kernel),"           \
155                                                 "384k(MiniFS),"         \
156                                                 "-(FS)"                 \
157                                         ";"                             \
158                                         "atmel_nand:"                   \
159                                                 "1M(emergency),"        \
160                                                 "-(data)"
161 /*
162  * Hardware drivers
163  */
164 #define CONFIG_USB_ATMEL
165 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
166 #define CONFIG_USB_OHCI_NEW
167 #define CONFIG_AT91C_PQFP_UHPBUG
168 #define CONFIG_USB_STORAGE
169 #define CONFIG_DOS_PARTITION
170 #define CONFIG_ISO_PARTITION
171 #define CONFIG_EFI_PARTITION
172
173 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      1
174 #define CONFIG_SYS_USB_OHCI_CPU_INIT
175 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00300000
176 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91rm9200"
177
178 /*
179  * UART/CONSOLE
180  */
181
182 #define CONFIG_BAUDRATE 115200
183 #define CONFIG_ATMEL_USART
184 #define CONFIG_USART_BASE       ATMEL_BASE_DBGU
185 #define CONFIG_USART_ID         0/* ignored in arm */
186
187 /*
188  * network
189  */
190
191 #define CONFIG_NET_RETRY_COUNT          10
192 #define CONFIG_RESET_PHY_R              1
193
194 #define CONFIG_DRIVER_AT91EMAC          1
195 #define CONFIG_DRIVER_AT91EMAC_QUIET    1
196 #define CONFIG_SYS_RX_ETH_BUFFER        8
197 #define CONFIG_MII                      1
198
199 /*
200  * BOOTP options
201  */
202 #define CONFIG_BOOTP_BOOTFILESIZE
203 #define CONFIG_BOOTP_BOOTPATH
204 #define CONFIG_BOOTP_GATEWAY
205 #define CONFIG_BOOTP_HOSTNAME
206
207 /*
208  * I2C-Bus
209  */
210
211 #define CONFIG_SYS_I2C
212 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
213 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
214 #define CONFIG_SYS_I2C_SOFT_SLAVE       0
215
216 /* Software  I2C driver configuration */
217
218 #define AT91_PIN_SDA                    (1<<25)         /* AT91C_PIO_PA25 */
219 #define AT91_PIN_SCL                    (1<<26)         /* AT91C_PIO_PA26 */
220
221 #define CONFIG_SYS_I2C_INIT_BOARD
222
223 #define I2C_INIT        i2c_init_board();
224 #define I2C_ACTIVE      writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
225 #define I2C_TRISTATE    writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
226 #define I2C_READ        ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
227 #define I2C_SDA(bit)                                            \
228         if (bit)                                                \
229                 writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr);      \
230         else                                                    \
231                 writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
232 #define I2C_SCL(bit)                                            \
233         if (bit)                                                \
234                 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr);     \
235         else                                                    \
236                 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
237
238 #define I2C_DELAY       udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED)
239
240 /* I2C-RTC */
241
242 #ifdef CONFIG_CMD_DATE
243 #define CONFIG_RTC_DS1338
244 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
245 #endif
246
247 /* EEPROM */
248
249 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
250 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
251
252 /* FLASH organization */
253
254 /*  NOR-FLASH */
255 #define CONFIG_FLASH_SHOW_PROGRESS      45
256
257 #define CONFIG_FLASH_CFI_DRIVER 1
258
259 #define PHYS_FLASH_1                    0x10000000
260 #define PHYS_FLASH_SIZE                 0x01000000  /* 16 megs main flash */
261 #define CONFIG_SYS_FLASH_CFI            1
262 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
263
264 #define CONFIG_SYS_FLASH_PROTECTION     1
265 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
266 #define CONFIG_SYS_MAX_FLASH_BANKS      1
267 #define CONFIG_SYS_MAX_FLASH_SECT       512
268 #define CONFIG_SYS_FLASH_ERASE_TOUT     6000
269 #define CONFIG_SYS_FLASH_WRITE_TOUT     2000
270
271 /* NAND */
272
273 #define CONFIG_SYS_MAX_NAND_DEVICE      1
274 #define CONFIG_SYS_NAND_BASE            0x40000000
275 #define CONFIG_SYS_NAND_DBW_8           1
276
277 /* Status LED's */
278
279 #define CONFIG_STATUS_LED               1
280 #define CONFIG_BOARD_SPECIFIC_LED       1
281
282 #define STATUS_LED_BOOT                 1
283 #define STATUS_LED_ACTIVE               0
284
285 #define STATUS_LED_BIT                  1       /* AT91C_PIO_PD0 green LED */
286 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
287 #define STATUS_LED_STATE                STATUS_LED_OFF          /* BLINKING */
288 #define STATUS_LED_BIT1                 2       /* AT91C_PIO_PD1  red LED */
289 #define STATUS_LED_STATE1               STATUS_LED_ON           /* BLINKING */
290 #define STATUS_LED_PERIOD1              (CONFIG_SYS_HZ / 4)
291
292 #define CONFIG_VIDEO                    1
293
294 /* Options */
295
296 #ifdef CONFIG_VIDEO
297
298 #define CONFIG_VIDEO_VCXK                       1
299
300 #define CONFIG_SPLASH_SCREEN                    1
301
302 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       4
303 #define CONFIG_SYS_VCXK_BASE    0x30000000
304
305 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         (1<<3)
306 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        piob
307 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         odr
308
309 #define CONFIG_SYS_VCXK_ENABLE_PIN              (1<<5)
310 #define CONFIG_SYS_VCXK_ENABLE_PORT             piob
311 #define CONFIG_SYS_VCXK_ENABLE_DDR              oer
312
313 #define CONFIG_SYS_VCXK_REQUEST_PIN             (1<<2)
314 #define CONFIG_SYS_VCXK_REQUEST_PORT            piob
315 #define CONFIG_SYS_VCXK_REQUEST_DDR             oer
316
317 #define CONFIG_SYS_VCXK_INVERT_PIN              (1<<4)
318 #define CONFIG_SYS_VCXK_INVERT_PORT             piob
319 #define CONFIG_SYS_VCXK_INVERT_DDR              oer
320
321 #define CONFIG_SYS_VCXK_RESET_PIN               (1<<6)
322 #define CONFIG_SYS_VCXK_RESET_PORT              piob
323 #define CONFIG_SYS_VCXK_RESET_DDR               oer
324
325 #endif  /* CONFIG_VIDEO */
326
327 /* Environment */
328
329 #define CONFIG_BOOTDELAY                5
330
331 #define CONFIG_ENV_IS_IN_FLASH          1
332 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x80000)
333 #define CONFIG_ENV_SIZE                 0x20000 /* sectors are 128K here */
334
335 #define CONFIG_BAUDRATE                 115200
336
337 #define CONFIG_BOOTCOMMAND              "run nfsboot"
338
339 #define CONFIG_NFSBOOTCOMMAND                                           \
340                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
341                 "run bootargsdefaults;"                                 \
342                 "set bootargs $(bootargs) boot=nfs "                    \
343                 ";echo $(bootargs)"                                     \
344         ";bootm"
345
346 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
347         "displaywidth=256\0"                                            \
348         "displayheight=512\0"                                           \
349         "displaybsteps=1023\0"                                          \
350         "ubootaddr=10000000\0"                                          \
351         "splashimage=100A0000\0"                                        \
352         "kerneladdr=100C0000\0"                                         \
353         "kernelsize=00400000\0"                                         \
354         "rootfsaddr=10520000\0"                                         \
355         "copy_addr=21200000\0"                                          \
356         "rootfssize=00AE0000\0"                                         \
357         "mtdids=" MTDIDS_DEFAULT "\0"                                   \
358         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
359         "bootargsdefaults=set bootargs "                                \
360                 "console=ttyS0,115200 "                                 \
361                 "video=vcxk_fb:xres:${displaywidth},"                   \
362                         "yres:${displayheight},"                        \
363                         "bres:${displaybsteps} "                        \
364                 "mem=62M "                                              \
365                 "panic=10 "                                             \
366                 "uboot=\\\"${ver}\\\" "                                 \
367                 "\0"                                                    \
368         "update_kernel=protect off $(kerneladdr) +$(kernelsize);"       \
369                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
370                 "erase $(kerneladdr) +$(kernelsize);"                   \
371                 "cp.b $(fileaddr) $(kerneladdr) $(filesize);"           \
372                 "protect on $(kerneladdr) +$(kernelsize)"               \
373                 "\0"                                                    \
374         "update_root=protect off $(rootfsaddr) +$(rootfssize);"         \
375                 "dhcp $(copy_addr) rfs;"                                \
376                 "erase $(rootfsaddr) +$(rootfssize);"                   \
377                 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);"           \
378                 "\0"                                                    \
379         "update_uboot=protect off 10000000 1007FFFF;"                   \
380                 "dhcp $(copy_addr) u-boot_eb_cpux9k2;"                  \
381                 "erase 10000000 1007FFFF;"                              \
382                 "cp.b $(fileaddr) $(ubootaddr) $(filesize);"            \
383                 "protect on 10000000 1007FFFF;reset\0"                  \
384         "update_splash=protect off $(splashimage) +20000;"              \
385                 "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;"              \
386                 "erase $(splashimage) +20000;"                          \
387                 "cp.b $(fileaddr) $(splashimage) $(filesize);"          \
388                 "protect on $(splashimage) +20000;reset\0"              \
389         "emergency=run bootargsdefaults;"                               \
390                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
391                 ";bootm $(kerneladdr)\0"                                \
392         "netemergency=run bootargsdefaults;"                            \
393                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
394                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
395                 ";bootm $(copy_addr)\0"                                 \
396         "norboot=run bootargsdefaults;"                                 \
397                 "set bootargs $(bootargs) root=initramfs boot=local "   \
398                 ";bootm $(kerneladdr)\0"                                \
399         "nandboot=run bootargsdefaults;"                                \
400                 "set bootargs $(bootargs) root=initramfs boot=nand "    \
401                 ";bootm $(kerneladdr)\0"                                \
402         " "
403
404 /*--------------------------------------------------------------------------*/
405
406 #endif
407
408 /* EOF */