1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
5 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
8 #ifndef _CONFIG_EB_CPU5282_H_
9 #define _CONFIG_EB_CPU5282_H_
11 /*----------------------------------------------------------------------*
12 * High Level Configuration Options (easy to change) *
13 *----------------------------------------------------------------------*/
15 #define CFG_SYS_UART_PORT (0)
17 /*----------------------------------------------------------------------*
19 *----------------------------------------------------------------------*/
21 #define STATUS_LED_ACTIVE 0
23 /*----------------------------------------------------------------------*
24 * Configuration for environment *
25 * Environment is in the second sector of the first 256k of flash *
26 *----------------------------------------------------------------------*/
28 /*#define CFG_SYS_DRAM_TEST 1 */
29 #undef CFG_SYS_DRAM_TEST
31 /*----------------------------------------------------------------------*
32 * Clock and PLL Configuration *
33 *----------------------------------------------------------------------*/
34 #define CFG_SYS_CLK 80000000 /* 8MHz * 8 */
36 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
38 #define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
39 #define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
41 /*----------------------------------------------------------------------*
43 *----------------------------------------------------------------------*/
46 #define CONFIG_OVERWRITE_ETHADDR_ONCE
49 /*-------------------------------------------------------------------------
50 * Low Level Configuration Settings
51 * (address mappings, register initial values, etc.)
52 * You should know what you are doing if you make changes here.
53 *-----------------------------------------------------------------------*/
55 #define CFG_SYS_MBAR 0x40000000
57 /*-----------------------------------------------------------------------
58 * Definitions for initial stack pointer and data area (in DPRAM)
59 *-----------------------------------------------------------------------*/
61 #define CFG_SYS_INIT_RAM_ADDR 0x20000000
62 #define CFG_SYS_INIT_RAM_SIZE 0x10000
64 /*-----------------------------------------------------------------------
65 * Start addresses for the final memory configuration
66 * (Set up by the startup code)
67 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
69 #define CFG_SYS_SDRAM_BASE0 0x00000000
70 #define CFG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
72 #define CFG_SYS_SDRAM_BASE CFG_SYS_SDRAM_BASE0
73 #define CFG_SYS_SDRAM_SIZE CFG_SYS_SDRAM_SIZE0
76 * For booting Linux, the board info and command line data
77 * have to be in the first 8 MB of memory, since this is
78 * the maximum mapped by the Linux kernel during initialization ??
80 #define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
82 /*-----------------------------------------------------------------------
86 #define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
87 #define CFG_SYS_INT_FLASH_BASE 0xF0000000
88 #define CFG_SYS_INT_FLASH_ENABLE 0x21
90 #define CFG_SYS_FLASH_SIZE 16*1024*1024
92 #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
94 /*-----------------------------------------------------------------------
98 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
99 CFG_SYS_INIT_RAM_SIZE - 8)
100 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
101 CFG_SYS_INIT_RAM_SIZE - 4)
102 #define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
103 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
104 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
105 CF_ACR_EN | CF_ACR_SM_ALL)
106 #define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
107 CF_CACR_CEIB | CF_CACR_DBWE | \
110 /*-----------------------------------------------------------------------
111 * Memory bank definitions
114 #define CFG_SYS_CS0_BASE 0xFF000000
115 #define CFG_SYS_CS0_CTRL 0x00001980
116 #define CFG_SYS_CS0_MASK 0x00FF0001
118 #define CFG_SYS_CS2_BASE 0xE0000000
119 #define CFG_SYS_CS2_CTRL 0x00001980
120 #define CFG_SYS_CS2_MASK 0x000F0001
122 #define CFG_SYS_CS3_BASE 0xE0100000
123 #define CFG_SYS_CS3_CTRL 0x00001980
124 #define CFG_SYS_CS3_MASK 0x000F0001
126 /*-----------------------------------------------------------------------
129 #define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
130 #define CFG_SYS_PADDR 0x0000000
131 #define CFG_SYS_PADAT 0x0000000
133 #define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
134 #define CFG_SYS_PBDDR 0x0000000
135 #define CFG_SYS_PBDAT 0x0000000
137 #define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
139 #define CFG_SYS_PASPAR 0x0F0F
140 #define CFG_SYS_PEHLPAR 0xC0
141 #define CFG_SYS_PUAPAR 0x0F
142 #define CFG_SYS_DDRUA 0x05
143 #define CFG_SYS_PJPAR 0xFF
145 #endif /* _CONFIG_M5282EVB_H */
146 /*---------------------------------------------------------------------*/