include/configs/eb_cpu5282.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   4  *
   5  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   6  */
   7
   8 #ifndef _CONFIG_EB_CPU5282_H_
   9 #define _CONFIG_EB_CPU5282_H_
  10
  11 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  12
  13 /*----------------------------------------------------------------------*
  14  * High Level Configuration Options (easy to change)                    *
  15  *----------------------------------------------------------------------*/
  16
  17 #define CONFIG_SYS_UART_PORT            (0)
  18
  19 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  20
  21 /*----------------------------------------------------------------------*
  22  * Options                                                              *
  23  *----------------------------------------------------------------------*/
  24
  25 #define STATUS_LED_ACTIVE               0
  26
  27 /*----------------------------------------------------------------------*
  28  * Configuration for environment                                        *
  29  * Environment is in the second sector of the first 256k of flash       *
  30  *----------------------------------------------------------------------*/
  31
  32 #define CONFIG_MCFTMR
  33
  34 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size      */
  35 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  36
  37 /*#define CONFIG_SYS_DRAM_TEST          1 */
  38 #undef CONFIG_SYS_DRAM_TEST
  39
  40 /*----------------------------------------------------------------------*
  41  * Clock and PLL Configuration                                          *
  42  *----------------------------------------------------------------------*/
  43 #define CONFIG_SYS_CLK                  80000000      /* 8MHz * 8 */
  44
  45 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  46
  47 #define CONFIG_SYS_MFD          0x02    /* PLL Multiplication Factor Devider */
  48 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
  49
  50 /*----------------------------------------------------------------------*
  51  * Network                                                              *
  52  *----------------------------------------------------------------------*/
  53
  54 #ifdef CONFIG_MCFFEC
  55 #define CONFIG_MII_INIT                 1
  56 #define CONFIG_SYS_DISCOVER_PHY
  57 #define CONFIG_SYS_RX_ETH_BUFFER        8
  58 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  59 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  60 #endif
  61
  62 /*-------------------------------------------------------------------------
  63  * Low Level Configuration Settings
  64  * (address mappings, register initial values, etc.)
  65  * You should know what you are doing if you make changes here.
  66  *-----------------------------------------------------------------------*/
  67
  68 #define CONFIG_SYS_MBAR                 0x40000000
  69
  70 /*-----------------------------------------------------------------------
  71  * Definitions for initial stack pointer and data area (in DPRAM)
  72  *-----------------------------------------------------------------------*/
  73
  74 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  75 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  76 #define CONFIG_SYS_GBL_DATA_OFFSET      \
  77         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  78 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  79
  80 /*-----------------------------------------------------------------------
  81  * Start addresses for the final memory configuration
  82  * (Set up by the startup code)
  83  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  84  */
  85 #define CONFIG_SYS_SDRAM_BASE0          0x00000000
  86 #define CONFIG_SYS_SDRAM_SIZE0          16      /* SDRAM size in MB */
  87
  88 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE0
  89 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE0
  90
  91 #define CONFIG_SYS_MONITOR_LEN          0x20000
  92 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
  93
  94 /*
  95  * For booting Linux, the board info and command line data
  96  * have to be in the first 8 MB of memory, since this is
  97  * the maximum mapped by the Linux kernel during initialization ??
  98  */
  99 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 100
 101 /*-----------------------------------------------------------------------
 102  * FLASH organization
 103  */
 104 #define CONFIG_FLASH_SHOW_PROGRESS      45
 105
 106 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 107 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
 108 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 109
 110 #define CONFIG_SYS_MAX_FLASH_SECT       128
 111 #define CONFIG_SYS_FLASH_ERASE_TOUT     10000000
 112
 113 #define CONFIG_SYS_FLASH_SIZE           16*1024*1024
 114 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 115
 116 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 117
 118 /*-----------------------------------------------------------------------
 119  * Cache Configuration
 120  */
 121
 122 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 123                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 124 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 125                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 126 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 127 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 128                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 129                                          CF_ACR_EN | CF_ACR_SM_ALL)
 130 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 131                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 132                                          CF_CACR_EUSP)
 133
 134 /*-----------------------------------------------------------------------
 135  * Memory bank definitions
 136  */
 137
 138 #define CONFIG_SYS_CS0_BASE             0xFF000000
 139 #define CONFIG_SYS_CS0_CTRL             0x00001980
 140 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 141
 142 #define CONFIG_SYS_CS2_BASE             0xE0000000
 143 #define CONFIG_SYS_CS2_CTRL             0x00001980
 144 #define CONFIG_SYS_CS2_MASK             0x000F0001
 145
 146 #define CONFIG_SYS_CS3_BASE             0xE0100000
 147 #define CONFIG_SYS_CS3_CTRL             0x00001980
 148 #define CONFIG_SYS_CS3_MASK             0x000F0001
 149
 150 /*-----------------------------------------------------------------------
 151  * Port configuration
 152  */
 153 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 154 #define CONFIG_SYS_PADDR                0x0000000
 155 #define CONFIG_SYS_PADAT                0x0000000
 156
 157 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 158 #define CONFIG_SYS_PBDDR                0x0000000
 159 #define CONFIG_SYS_PBDAT                0x0000000
 160
 161 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 162 #define CONFIG_SYS_PCDDR                0x0000000
 163 #define CONFIG_SYS_PCDAT                0x0000000
 164
 165 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 166 #define CONFIG_SYS_PCDDR                0x0000000
 167 #define CONFIG_SYS_PCDAT                0x0000000
 168
 169 #define CONFIG_SYS_PASPAR               0x0F0F
 170 #define CONFIG_SYS_PEHLPAR              0xC0
 171 #define CONFIG_SYS_PUAPAR               0x0F
 172 #define CONFIG_SYS_DDRUA                0x05
 173 #define CONFIG_SYS_PJPAR                0xFF
 174
 175 /*-----------------------------------------------------------------------
 176  * I2C
 177  */
 178
 179 #ifdef CONFIG_CMD_DATE
 180 #define CONFIG_RTC_DS1338
 181 #define CONFIG_I2C_RTC_ADDR             0x68
 182 #endif
 183
 184 /*-----------------------------------------------------------------------
 185  * VIDEO configuration
 186  */
 187
 188 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 189 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 190 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS2_BASE
 191
 192 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 193 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 194 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 195
 196 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 197 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 198 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 199
 200 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 201 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 202 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 203
 204 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 205 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 206 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 207
 208 #endif  /* _CONFIG_M5282EVB_H */
 209 /*---------------------------------------------------------------------*/