include/configs/eb_cpu5282.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   4  *
   5  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   6  */
   7
   8 #ifndef _CONFIG_EB_CPU5282_H_
   9 #define _CONFIG_EB_CPU5282_H_
  10
  11 /*----------------------------------------------------------------------*
  12  * High Level Configuration Options (easy to change)                    *
  13  *----------------------------------------------------------------------*/
  14
  15 #define CFG_SYS_UART_PORT               (0)
  16
  17 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  18
  19 /*----------------------------------------------------------------------*
  20  * Options                                                              *
  21  *----------------------------------------------------------------------*/
  22
  23 #define STATUS_LED_ACTIVE               0
  24
  25 /*----------------------------------------------------------------------*
  26  * Configuration for environment                                        *
  27  * Environment is in the second sector of the first 256k of flash       *
  28  *----------------------------------------------------------------------*/
  29
  30 /*#define CFG_SYS_DRAM_TEST             1 */
  31 #undef CFG_SYS_DRAM_TEST
  32
  33 /*----------------------------------------------------------------------*
  34  * Clock and PLL Configuration                                          *
  35  *----------------------------------------------------------------------*/
  36 #define CFG_SYS_CLK                     80000000      /* 8MHz * 8 */
  37
  38 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  39
  40 #define CFG_SYS_MFD             0x02    /* PLL Multiplication Factor Devider */
  41 #define CFG_SYS_RFD             0x00    /* PLL Reduce Frecuency Devider */
  42
  43 /*----------------------------------------------------------------------*
  44  * Network                                                              *
  45  *----------------------------------------------------------------------*/
  46
  47 #ifdef CONFIG_MCFFEC
  48 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  49 #endif
  50
  51 /*-------------------------------------------------------------------------
  52  * Low Level Configuration Settings
  53  * (address mappings, register initial values, etc.)
  54  * You should know what you are doing if you make changes here.
  55  *-----------------------------------------------------------------------*/
  56
  57 #define CFG_SYS_MBAR                    0x40000000
  58
  59 /*-----------------------------------------------------------------------
  60  * Definitions for initial stack pointer and data area (in DPRAM)
  61  *-----------------------------------------------------------------------*/
  62
  63 #define CFG_SYS_INIT_RAM_ADDR   0x20000000
  64 #define CFG_SYS_INIT_RAM_SIZE   0x10000
  65
  66 /*-----------------------------------------------------------------------
  67  * Start addresses for the final memory configuration
  68  * (Set up by the startup code)
  69  * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  70  */
  71 #define CFG_SYS_SDRAM_BASE0             0x00000000
  72 #define CFG_SYS_SDRAM_SIZE0             16      /* SDRAM size in MB */
  73
  74 #define CFG_SYS_SDRAM_BASE              CFG_SYS_SDRAM_BASE0
  75 #define CFG_SYS_SDRAM_SIZE              CFG_SYS_SDRAM_SIZE0
  76
  77 /*
  78  * For booting Linux, the board info and command line data
  79  * have to be in the first 8 MB of memory, since this is
  80  * the maximum mapped by the Linux kernel during initialization ??
  81  */
  82 #define CFG_SYS_BOOTMAPSZ       (8 << 20) /* Initial Memory map for Linux */
  83
  84 /*-----------------------------------------------------------------------
  85  * FLASH organization
  86  */
  87
  88 #define CFG_SYS_FLASH_BASE              CFG_SYS_CS0_BASE
  89 #define CFG_SYS_INT_FLASH_BASE  0xF0000000
  90 #define CFG_SYS_INT_FLASH_ENABLE        0x21
  91
  92 #define CFG_SYS_FLASH_SIZE              16*1024*1024
  93
  94 #define CFG_SYS_FLASH_BANKS_LIST        { CFG_SYS_FLASH_BASE }
  95
  96 /*-----------------------------------------------------------------------
  97  * Cache Configuration
  98  */
  99
 100 #define ICACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
 101                                          CFG_SYS_INIT_RAM_SIZE - 8)
 102 #define DCACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
 103                                          CFG_SYS_INIT_RAM_SIZE - 4)
 104 #define CFG_SYS_ICACHE_INV              (CF_CACR_CINV + CF_CACR_DCM)
 105 #define CFG_SYS_CACHE_ACR0              (CFG_SYS_SDRAM_BASE | \
 106                                          CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 107                                          CF_ACR_EN | CF_ACR_SM_ALL)
 108 #define CFG_SYS_CACHE_ICACR             (CF_CACR_CENB | CF_CACR_DISD | \
 109                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 110                                          CF_CACR_EUSP)
 111
 112 /*-----------------------------------------------------------------------
 113  * Memory bank definitions
 114  */
 115
 116 #define CFG_SYS_CS0_BASE                0xFF000000
 117 #define CFG_SYS_CS0_CTRL                0x00001980
 118 #define CFG_SYS_CS0_MASK                0x00FF0001
 119
 120 #define CFG_SYS_CS2_BASE                0xE0000000
 121 #define CFG_SYS_CS2_CTRL                0x00001980
 122 #define CFG_SYS_CS2_MASK                0x000F0001
 123
 124 #define CFG_SYS_CS3_BASE                0xE0100000
 125 #define CFG_SYS_CS3_CTRL                0x00001980
 126 #define CFG_SYS_CS3_MASK                0x000F0001
 127
 128 /*-----------------------------------------------------------------------
 129  * Port configuration
 130  */
 131 #define CFG_SYS_PACNT           0x0000000       /* Port A D[31:24] */
 132 #define CFG_SYS_PADDR           0x0000000
 133 #define CFG_SYS_PADAT           0x0000000
 134
 135 #define CFG_SYS_PBCNT           0x0000000       /* Port B D[23:16] */
 136 #define CFG_SYS_PBDDR           0x0000000
 137 #define CFG_SYS_PBDAT           0x0000000
 138
 139 #define CFG_SYS_PDCNT           0x0000000       /* Port D D[07:00] */
 140
 141 #define CFG_SYS_PASPAR          0x0F0F
 142 #define CFG_SYS_PEHLPAR         0xC0
 143 #define CFG_SYS_PUAPAR          0x0F
 144 #define CFG_SYS_DDRUA           0x05
 145 #define CFG_SYS_PJPAR           0xFF
 146
 147 /*-----------------------------------------------------------------------
 148  * I2C
 149  */
 150
 151 #ifdef CONFIG_CMD_DATE
 152 #define CONFIG_I2C_RTC_ADDR             0x68
 153 #endif
 154
 155 #endif  /* _CONFIG_M5282EVB_H */
 156 /*---------------------------------------------------------------------*/