include/configs/eb_cpu5282.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   4  *
   5  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   6  */
   7
   8 #ifndef _CONFIG_EB_CPU5282_H_
   9 #define _CONFIG_EB_CPU5282_H_
  10
  11 /*----------------------------------------------------------------------*
  12  * High Level Configuration Options (easy to change)                    *
  13  *----------------------------------------------------------------------*/
  14
  15 #define CONFIG_SYS_UART_PORT            (0)
  16
  17 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  18
  19 /*----------------------------------------------------------------------*
  20  * Options                                                              *
  21  *----------------------------------------------------------------------*/
  22
  23 #define STATUS_LED_ACTIVE               0
  24
  25 /*----------------------------------------------------------------------*
  26  * Configuration for environment                                        *
  27  * Environment is in the second sector of the first 256k of flash       *
  28  *----------------------------------------------------------------------*/
  29
  30 /*#define CONFIG_SYS_DRAM_TEST          1 */
  31 #undef CONFIG_SYS_DRAM_TEST
  32
  33 /*----------------------------------------------------------------------*
  34  * Clock and PLL Configuration                                          *
  35  *----------------------------------------------------------------------*/
  36 #define CONFIG_SYS_CLK                  80000000      /* 8MHz * 8 */
  37
  38 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  39
  40 #define CONFIG_SYS_MFD          0x02    /* PLL Multiplication Factor Devider */
  41 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
  42
  43 /*----------------------------------------------------------------------*
  44  * Network                                                              *
  45  *----------------------------------------------------------------------*/
  46
  47 #ifdef CONFIG_MCFFEC
  48 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  49 #endif
  50
  51 /*-------------------------------------------------------------------------
  52  * Low Level Configuration Settings
  53  * (address mappings, register initial values, etc.)
  54  * You should know what you are doing if you make changes here.
  55  *-----------------------------------------------------------------------*/
  56
  57 #define CONFIG_SYS_MBAR                 0x40000000
  58
  59 /*-----------------------------------------------------------------------
  60  * Definitions for initial stack pointer and data area (in DPRAM)
  61  *-----------------------------------------------------------------------*/
  62
  63 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  64 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  65
  66 /*-----------------------------------------------------------------------
  67  * Start addresses for the final memory configuration
  68  * (Set up by the startup code)
  69  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  70  */
  71 #define CONFIG_SYS_SDRAM_BASE0          0x00000000
  72 #define CONFIG_SYS_SDRAM_SIZE0          16      /* SDRAM size in MB */
  73
  74 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE0
  75 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE0
  76
  77 #define CONFIG_SYS_MONITOR_LEN          0x20000
  78
  79 /*
  80  * For booting Linux, the board info and command line data
  81  * have to be in the first 8 MB of memory, since this is
  82  * the maximum mapped by the Linux kernel during initialization ??
  83  */
  84 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
  85
  86 /*-----------------------------------------------------------------------
  87  * FLASH organization
  88  */
  89 #define CONFIG_FLASH_SHOW_PROGRESS      45
  90
  91 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
  92 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
  93 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
  94
  95 #define CONFIG_SYS_FLASH_SIZE           16*1024*1024
  96
  97 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
  98
  99 /*-----------------------------------------------------------------------
 100  * Cache Configuration
 101  */
 102
 103 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 104                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 105 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 106                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 107 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 108 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 109                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 110                                          CF_ACR_EN | CF_ACR_SM_ALL)
 111 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 112                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 113                                          CF_CACR_EUSP)
 114
 115 /*-----------------------------------------------------------------------
 116  * Memory bank definitions
 117  */
 118
 119 #define CONFIG_SYS_CS0_BASE             0xFF000000
 120 #define CONFIG_SYS_CS0_CTRL             0x00001980
 121 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 122
 123 #define CONFIG_SYS_CS2_BASE             0xE0000000
 124 #define CONFIG_SYS_CS2_CTRL             0x00001980
 125 #define CONFIG_SYS_CS2_MASK             0x000F0001
 126
 127 #define CONFIG_SYS_CS3_BASE             0xE0100000
 128 #define CONFIG_SYS_CS3_CTRL             0x00001980
 129 #define CONFIG_SYS_CS3_MASK             0x000F0001
 130
 131 /*-----------------------------------------------------------------------
 132  * Port configuration
 133  */
 134 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 135 #define CONFIG_SYS_PADDR                0x0000000
 136 #define CONFIG_SYS_PADAT                0x0000000
 137
 138 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 139 #define CONFIG_SYS_PBDDR                0x0000000
 140 #define CONFIG_SYS_PBDAT                0x0000000
 141
 142 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 143 #define CONFIG_SYS_PCDDR                0x0000000
 144 #define CONFIG_SYS_PCDAT                0x0000000
 145
 146 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 147 #define CONFIG_SYS_PCDDR                0x0000000
 148 #define CONFIG_SYS_PCDAT                0x0000000
 149
 150 #define CONFIG_SYS_PASPAR               0x0F0F
 151 #define CONFIG_SYS_PEHLPAR              0xC0
 152 #define CONFIG_SYS_PUAPAR               0x0F
 153 #define CONFIG_SYS_DDRUA                0x05
 154 #define CONFIG_SYS_PJPAR                0xFF
 155
 156 /*-----------------------------------------------------------------------
 157  * I2C
 158  */
 159
 160 #ifdef CONFIG_CMD_DATE
 161 #define CONFIG_RTC_DS1338
 162 #define CONFIG_I2C_RTC_ADDR             0x68
 163 #endif
 164
 165 /*-----------------------------------------------------------------------
 166  * VIDEO configuration
 167  */
 168
 169 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 170 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 171 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS2_BASE
 172
 173 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 174 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 175 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 176
 177 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 178 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 179 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 180
 181 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 182 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 183 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 184
 185 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 186 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 187 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 188
 189 #endif  /* _CONFIG_M5282EVB_H */
 190 /*---------------------------------------------------------------------*/