2 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
4 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _CONFIG_EB_CPU5282_H_
10 #define _CONFIG_EB_CPU5282_H_
12 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
14 /*----------------------------------------------------------------------*
15 * High Level Configuration Options (easy to change) *
16 *----------------------------------------------------------------------*/
18 #define CONFIG_MISC_INIT_R
20 #define CONFIG_MCFUART
21 #define CONFIG_SYS_UART_PORT (0)
23 #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
25 #define CONFIG_BOOTCOMMAND "printenv"
27 /*----------------------------------------------------------------------*
29 *----------------------------------------------------------------------*/
31 #define CONFIG_BOOT_RETRY_TIME -1
32 #define CONFIG_RESET_TO_RETRY
33 #define CONFIG_SPLASH_SCREEN
35 #define CONFIG_HW_WATCHDOG
37 #define STATUS_LED_ACTIVE 0
39 /*----------------------------------------------------------------------*
40 * Configuration for environment *
41 * Environment is in the second sector of the first 256k of flash *
42 *----------------------------------------------------------------------*/
44 #define CONFIG_ENV_ADDR 0xFF040000
45 #define CONFIG_ENV_SECT_SIZE 0x00020000
46 #define CONFIG_ENV_IS_IN_FLASH 1
51 #define CONFIG_BOOTP_BOOTFILESIZE
52 #define CONFIG_BOOTP_BOOTPATH
53 #define CONFIG_BOOTP_GATEWAY
54 #define CONFIG_BOOTP_HOSTNAME
57 * Command line configuration.
59 #define CONFIG_CMDLINE_EDITING
60 #define CONFIG_CMD_DATE
64 #define CONFIG_SYS_LONGHELP 1
66 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
67 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
68 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
69 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
71 #define CONFIG_SYS_LOAD_ADDR 0x20000
73 #define CONFIG_SYS_MEMTEST_START 0x100000
74 #define CONFIG_SYS_MEMTEST_END 0x400000
75 /*#define CONFIG_SYS_DRAM_TEST 1 */
76 #undef CONFIG_SYS_DRAM_TEST
78 /*----------------------------------------------------------------------*
79 * Clock and PLL Configuration *
80 *----------------------------------------------------------------------*/
81 #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
83 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
85 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
86 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
88 /*----------------------------------------------------------------------*
90 *----------------------------------------------------------------------*/
94 #define CONFIG_MII_INIT 1
95 #define CONFIG_SYS_DISCOVER_PHY
96 #define CONFIG_SYS_RX_ETH_BUFFER 8
97 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
99 #define CONFIG_SYS_FEC0_PINMUX 0
100 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
101 #define MCFFEC_TOUT_LOOP 50000
103 #define CONFIG_OVERWRITE_ETHADDR_ONCE
105 /*-------------------------------------------------------------------------
106 * Low Level Configuration Settings
107 * (address mappings, register initial values, etc.)
108 * You should know what you are doing if you make changes here.
109 *-----------------------------------------------------------------------*/
111 #define CONFIG_SYS_MBAR 0x40000000
113 /*-----------------------------------------------------------------------
114 * Definitions for initial stack pointer and data area (in DPRAM)
115 *-----------------------------------------------------------------------*/
117 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
118 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
119 #define CONFIG_SYS_GBL_DATA_OFFSET \
120 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
121 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
123 /*-----------------------------------------------------------------------
124 * Start addresses for the final memory configuration
125 * (Set up by the startup code)
126 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
128 #define CONFIG_SYS_SDRAM_BASE0 0x00000000
129 #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
131 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
132 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
134 #define CONFIG_SYS_MONITOR_LEN 0x20000
135 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
136 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
139 * For booting Linux, the board info and command line data
140 * have to be in the first 8 MB of memory, since this is
141 * the maximum mapped by the Linux kernel during initialization ??
143 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
145 /*-----------------------------------------------------------------------
148 #define CONFIG_FLASH_SHOW_PROGRESS 45
150 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
151 #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
152 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21
154 #define CONFIG_SYS_MAX_FLASH_SECT 128
155 #define CONFIG_SYS_MAX_FLASH_BANKS 1
156 #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
157 #define CONFIG_SYS_FLASH_PROTECTION
159 #define CONFIG_SYS_FLASH_CFI
160 #define CONFIG_FLASH_CFI_DRIVER
161 #define CONFIG_SYS_FLASH_SIZE 16*1024*1024
162 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
164 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
166 /*-----------------------------------------------------------------------
167 * Cache Configuration
169 #define CONFIG_SYS_CACHELINE_SIZE 16
171 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
172 CONFIG_SYS_INIT_RAM_SIZE - 8)
173 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
174 CONFIG_SYS_INIT_RAM_SIZE - 4)
175 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
176 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
177 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
178 CF_ACR_EN | CF_ACR_SM_ALL)
179 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
180 CF_CACR_CEIB | CF_CACR_DBWE | \
183 /*-----------------------------------------------------------------------
184 * Memory bank definitions
187 #define CONFIG_SYS_CS0_BASE 0xFF000000
188 #define CONFIG_SYS_CS0_CTRL 0x00001980
189 #define CONFIG_SYS_CS0_MASK 0x00FF0001
191 #define CONFIG_SYS_CS2_BASE 0xE0000000
192 #define CONFIG_SYS_CS2_CTRL 0x00001980
193 #define CONFIG_SYS_CS2_MASK 0x000F0001
195 #define CONFIG_SYS_CS3_BASE 0xE0100000
196 #define CONFIG_SYS_CS3_CTRL 0x00001980
197 #define CONFIG_SYS_CS3_MASK 0x000F0001
199 /*-----------------------------------------------------------------------
202 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
203 #define CONFIG_SYS_PADDR 0x0000000
204 #define CONFIG_SYS_PADAT 0x0000000
206 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
207 #define CONFIG_SYS_PBDDR 0x0000000
208 #define CONFIG_SYS_PBDAT 0x0000000
210 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
211 #define CONFIG_SYS_PCDDR 0x0000000
212 #define CONFIG_SYS_PCDAT 0x0000000
214 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
215 #define CONFIG_SYS_PCDDR 0x0000000
216 #define CONFIG_SYS_PCDAT 0x0000000
218 #define CONFIG_SYS_PASPAR 0x0F0F
219 #define CONFIG_SYS_PEHLPAR 0xC0
220 #define CONFIG_SYS_PUAPAR 0x0F
221 #define CONFIG_SYS_DDRUA 0x05
222 #define CONFIG_SYS_PJPAR 0xFF
224 /*-----------------------------------------------------------------------
228 #define CONFIG_SYS_I2C
229 #define CONFIG_SYS_I2C_FSL
231 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
232 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
234 #define CONFIG_SYS_FSL_I2C_SPEED 100000
235 #define CONFIG_SYS_FSL_I2C_SLAVE 0
237 #ifdef CONFIG_CMD_DATE
238 #define CONFIG_RTC_DS1338
239 #define CONFIG_I2C_RTC_ADDR 0x68
242 /*-----------------------------------------------------------------------
243 * VIDEO configuration
247 #define CONFIG_VIDEO_VCXK 1
249 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
250 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
251 #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
253 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
254 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
255 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
257 #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
258 #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
259 #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
261 #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
262 #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
263 #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
265 #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
266 #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
267 #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
269 #endif /* CONFIG_VIDEO */
270 #endif /* _CONFIG_M5282EVB_H */
271 /*---------------------------------------------------------------------*/