2 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
4 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _CONFIG_EB_CPU5282_H_
10 #define _CONFIG_EB_CPU5282_H_
12 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
14 /*----------------------------------------------------------------------*
15 * High Level Configuration Options (easy to change) *
16 *----------------------------------------------------------------------*/
18 #define CONFIG_MISC_INIT_R
20 #define CONFIG_MCFUART
21 #define CONFIG_SYS_UART_PORT (0)
22 #define CONFIG_BAUDRATE 115200
24 #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
26 #define CONFIG_BOOTCOMMAND "printenv"
28 /*----------------------------------------------------------------------*
30 *----------------------------------------------------------------------*/
32 #define CONFIG_BOOT_RETRY_TIME -1
33 #define CONFIG_RESET_TO_RETRY
34 #define CONFIG_SPLASH_SCREEN
36 #define CONFIG_HW_WATCHDOG
38 #define CONFIG_STATUS_LED
39 #define CONFIG_BOARD_SPECIFIC_LED
40 #define STATUS_LED_ACTIVE 0
41 #define STATUS_LED_BIT 0x0008 /* Timer7 GPIO */
42 #define STATUS_LED_BOOT 0
43 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
44 #define STATUS_LED_STATE STATUS_LED_OFF
46 /*----------------------------------------------------------------------*
47 * Configuration for environment *
48 * Environment is in the second sector of the first 256k of flash *
49 *----------------------------------------------------------------------*/
51 #define CONFIG_ENV_ADDR 0xFF040000
52 #define CONFIG_ENV_SECT_SIZE 0x00020000
53 #define CONFIG_ENV_IS_IN_FLASH 1
58 #define CONFIG_BOOTP_BOOTFILESIZE
59 #define CONFIG_BOOTP_BOOTPATH
60 #define CONFIG_BOOTP_GATEWAY
61 #define CONFIG_BOOTP_HOSTNAME
64 * Command line configuration.
66 #define CONFIG_CMDLINE_EDITING
67 #include <config_cmd_default.h>
69 #undef CONFIG_CMD_LOADB
70 #define CONFIG_CMD_DATE
71 #define CONFIG_CMD_DHCP
72 #define CONFIG_CMD_I2C
73 #define CONFIG_CMD_LED
74 #define CONFIG_CMD_MII
75 #define CONFIG_CMD_NET
79 #define CONFIG_BOOTDELAY 5
80 #define CONFIG_SYS_PROMPT "\nEB+CPU5282> "
81 #define CONFIG_SYS_LONGHELP 1
83 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
84 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
85 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
86 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
88 #define CONFIG_SYS_LOAD_ADDR 0x20000
90 #define CONFIG_SYS_MEMTEST_START 0x100000
91 #define CONFIG_SYS_MEMTEST_END 0x400000
92 /*#define CONFIG_SYS_DRAM_TEST 1 */
93 #undef CONFIG_SYS_DRAM_TEST
95 /*----------------------------------------------------------------------*
96 * Clock and PLL Configuration *
97 *----------------------------------------------------------------------*/
98 #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
100 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
102 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
103 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
105 /*----------------------------------------------------------------------*
107 *----------------------------------------------------------------------*/
109 #define CONFIG_MCFFEC
111 #define CONFIG_MII_INIT 1
112 #define CONFIG_SYS_DISCOVER_PHY
113 #define CONFIG_SYS_RX_ETH_BUFFER 8
114 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
116 #define CONFIG_SYS_FEC0_PINMUX 0
117 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
118 #define MCFFEC_TOUT_LOOP 50000
120 #define CONFIG_OVERWRITE_ETHADDR_ONCE
122 /*-------------------------------------------------------------------------
123 * Low Level Configuration Settings
124 * (address mappings, register initial values, etc.)
125 * You should know what you are doing if you make changes here.
126 *-----------------------------------------------------------------------*/
128 #define CONFIG_SYS_MBAR 0x40000000
130 /*-----------------------------------------------------------------------
131 * Definitions for initial stack pointer and data area (in DPRAM)
132 *-----------------------------------------------------------------------*/
134 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
135 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
136 #define CONFIG_SYS_GBL_DATA_OFFSET \
137 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
138 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
140 /*-----------------------------------------------------------------------
141 * Start addresses for the final memory configuration
142 * (Set up by the startup code)
143 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
145 #define CONFIG_SYS_SDRAM_BASE0 0x00000000
146 #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
148 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
149 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
151 #define CONFIG_SYS_MONITOR_LEN 0x20000
152 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
153 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
156 * For booting Linux, the board info and command line data
157 * have to be in the first 8 MB of memory, since this is
158 * the maximum mapped by the Linux kernel during initialization ??
160 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
162 /*-----------------------------------------------------------------------
165 #define CONFIG_FLASH_SHOW_PROGRESS 45
167 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
168 #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
169 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21
171 #define CONFIG_SYS_MAX_FLASH_SECT 128
172 #define CONFIG_SYS_MAX_FLASH_BANKS 1
173 #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
174 #define CONFIG_SYS_FLASH_PROTECTION
176 #define CONFIG_SYS_FLASH_CFI
177 #define CONFIG_FLASH_CFI_DRIVER
178 #define CONFIG_SYS_FLASH_SIZE 16*1024*1024
179 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
181 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
183 /*-----------------------------------------------------------------------
184 * Cache Configuration
186 #define CONFIG_SYS_CACHELINE_SIZE 16
188 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
189 CONFIG_SYS_INIT_RAM_SIZE - 8)
190 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
191 CONFIG_SYS_INIT_RAM_SIZE - 4)
192 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
193 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
194 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
195 CF_ACR_EN | CF_ACR_SM_ALL)
196 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
197 CF_CACR_CEIB | CF_CACR_DBWE | \
200 /*-----------------------------------------------------------------------
201 * Memory bank definitions
204 #define CONFIG_SYS_CS0_BASE 0xFF000000
205 #define CONFIG_SYS_CS0_CTRL 0x00001980
206 #define CONFIG_SYS_CS0_MASK 0x00FF0001
208 #define CONFIG_SYS_CS2_BASE 0xE0000000
209 #define CONFIG_SYS_CS2_CTRL 0x00001980
210 #define CONFIG_SYS_CS2_MASK 0x000F0001
212 #define CONFIG_SYS_CS3_BASE 0xE0100000
213 #define CONFIG_SYS_CS3_CTRL 0x00001980
214 #define CONFIG_SYS_CS3_MASK 0x000F0001
216 /*-----------------------------------------------------------------------
219 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
220 #define CONFIG_SYS_PADDR 0x0000000
221 #define CONFIG_SYS_PADAT 0x0000000
223 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
224 #define CONFIG_SYS_PBDDR 0x0000000
225 #define CONFIG_SYS_PBDAT 0x0000000
227 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
228 #define CONFIG_SYS_PCDDR 0x0000000
229 #define CONFIG_SYS_PCDAT 0x0000000
231 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
232 #define CONFIG_SYS_PCDDR 0x0000000
233 #define CONFIG_SYS_PCDAT 0x0000000
235 #define CONFIG_SYS_PASPAR 0x0F0F
236 #define CONFIG_SYS_PEHLPAR 0xC0
237 #define CONFIG_SYS_PUAPAR 0x0F
238 #define CONFIG_SYS_DDRUA 0x05
239 #define CONFIG_SYS_PJPAR 0xFF
241 /*-----------------------------------------------------------------------
245 #define CONFIG_SYS_I2C
246 #define CONFIG_SYS_I2C_FSL
248 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
249 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
251 #define CONFIG_SYS_FSL_I2C_SPEED 100000
252 #define CONFIG_SYS_FSL_I2C_SLAVE 0
254 #ifdef CONFIG_CMD_DATE
255 #define CONFIG_RTC_DS1338
256 #define CONFIG_I2C_RTC_ADDR 0x68
259 /*-----------------------------------------------------------------------
260 * VIDEO configuration
266 #define CONFIG_VIDEO_VCXK 1
268 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
269 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
270 #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
272 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
273 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
274 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
276 #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
277 #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
278 #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
280 #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
281 #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
282 #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
284 #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
285 #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
286 #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
288 #endif /* CONFIG_VIDEO */
289 #endif /* _CONFIG_M5282EVB_H */
290 /*---------------------------------------------------------------------*/