include/configs/eb_cpu5282.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   4  *
   5  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   6  */
   7
   8 #ifndef _CONFIG_EB_CPU5282_H_
   9 #define _CONFIG_EB_CPU5282_H_
  10
  11 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  12
  13 /*----------------------------------------------------------------------*
  14  * High Level Configuration Options (easy to change)                    *
  15  *----------------------------------------------------------------------*/
  16
  17 #define CONFIG_MCFUART
  18 #define CONFIG_SYS_UART_PORT            (0)
  19
  20 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  21
  22 #define CONFIG_BOOTCOMMAND "printenv"
  23
  24 /*----------------------------------------------------------------------*
  25  * Options                                                              *
  26  *----------------------------------------------------------------------*/
  27
  28 #define CONFIG_BOOT_RETRY_TIME  -1
  29 #define CONFIG_RESET_TO_RETRY
  30 #define CONFIG_SPLASH_SCREEN
  31
  32 #define CONFIG_HW_WATCHDOG
  33
  34 #define STATUS_LED_ACTIVE               0
  35
  36 /*----------------------------------------------------------------------*
  37  * Configuration for environment                                        *
  38  * Environment is in the second sector of the first 256k of flash       *
  39  *----------------------------------------------------------------------*/
  40
  41 #define CONFIG_ENV_ADDR         0xFF040000
  42 #define CONFIG_ENV_SECT_SIZE    0x00020000
  43
  44 /*
  45  * BOOTP options
  46  */
  47 #define CONFIG_BOOTP_BOOTFILESIZE
  48
  49 /*
  50  * Command line configuration.
  51  */
  52
  53 #define CONFIG_MCFTMR
  54
  55 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size      */
  56 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  57
  58 #define CONFIG_SYS_LOAD_ADDR            0x20000
  59
  60 #define CONFIG_SYS_MEMTEST_START        0x100000
  61 #define CONFIG_SYS_MEMTEST_END          0x400000
  62 /*#define CONFIG_SYS_DRAM_TEST          1 */
  63 #undef CONFIG_SYS_DRAM_TEST
  64
  65 /*----------------------------------------------------------------------*
  66  * Clock and PLL Configuration                                          *
  67  *----------------------------------------------------------------------*/
  68 #define CONFIG_SYS_CLK                  80000000      /* 8MHz * 8 */
  69
  70 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  71
  72 #define CONFIG_SYS_MFD          0x02    /* PLL Multiplication Factor Devider */
  73 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
  74
  75 /*----------------------------------------------------------------------*
  76  * Network                                                              *
  77  *----------------------------------------------------------------------*/
  78
  79 #define CONFIG_MCFFEC
  80 #define CONFIG_MII_INIT                 1
  81 #define CONFIG_SYS_DISCOVER_PHY
  82 #define CONFIG_SYS_RX_ETH_BUFFER        8
  83 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  84
  85 #define CONFIG_SYS_FEC0_PINMUX          0
  86 #define CONFIG_SYS_FEC0_MIIBASE         CONFIG_SYS_FEC0_IOBASE
  87 #define MCFFEC_TOUT_LOOP                50000
  88
  89 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  90
  91 /*-------------------------------------------------------------------------
  92  * Low Level Configuration Settings
  93  * (address mappings, register initial values, etc.)
  94  * You should know what you are doing if you make changes here.
  95  *-----------------------------------------------------------------------*/
  96
  97 #define CONFIG_SYS_MBAR                 0x40000000
  98
  99 /*-----------------------------------------------------------------------
 100  * Definitions for initial stack pointer and data area (in DPRAM)
 101  *-----------------------------------------------------------------------*/
 102
 103 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 104 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
 105 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 106         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 107 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 108
 109 /*-----------------------------------------------------------------------
 110  * Start addresses for the final memory configuration
 111  * (Set up by the startup code)
 112  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 113  */
 114 #define CONFIG_SYS_SDRAM_BASE0          0x00000000
 115 #define CONFIG_SYS_SDRAM_SIZE0          16      /* SDRAM size in MB */
 116
 117 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE0
 118 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE0
 119
 120 #define CONFIG_SYS_MONITOR_LEN          0x20000
 121 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 122 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 123
 124 /*
 125  * For booting Linux, the board info and command line data
 126  * have to be in the first 8 MB of memory, since this is
 127  * the maximum mapped by the Linux kernel during initialization ??
 128  */
 129 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 130
 131 /*-----------------------------------------------------------------------
 132  * FLASH organization
 133  */
 134 #define CONFIG_FLASH_SHOW_PROGRESS      45
 135
 136 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 137 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
 138 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 139
 140 #define CONFIG_SYS_MAX_FLASH_SECT       128
 141 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 142 #define CONFIG_SYS_FLASH_ERASE_TOUT     10000000
 143
 144 #define CONFIG_SYS_FLASH_SIZE           16*1024*1024
 145 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 146
 147 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 148
 149 /*-----------------------------------------------------------------------
 150  * Cache Configuration
 151  */
 152 #define CONFIG_SYS_CACHELINE_SIZE       16
 153
 154 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 155                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 156 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 157                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 158 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 159 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 160                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 161                                          CF_ACR_EN | CF_ACR_SM_ALL)
 162 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 163                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 164                                          CF_CACR_EUSP)
 165
 166 /*-----------------------------------------------------------------------
 167  * Memory bank definitions
 168  */
 169
 170 #define CONFIG_SYS_CS0_BASE             0xFF000000
 171 #define CONFIG_SYS_CS0_CTRL             0x00001980
 172 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 173
 174 #define CONFIG_SYS_CS2_BASE             0xE0000000
 175 #define CONFIG_SYS_CS2_CTRL             0x00001980
 176 #define CONFIG_SYS_CS2_MASK             0x000F0001
 177
 178 #define CONFIG_SYS_CS3_BASE             0xE0100000
 179 #define CONFIG_SYS_CS3_CTRL             0x00001980
 180 #define CONFIG_SYS_CS3_MASK             0x000F0001
 181
 182 /*-----------------------------------------------------------------------
 183  * Port configuration
 184  */
 185 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 186 #define CONFIG_SYS_PADDR                0x0000000
 187 #define CONFIG_SYS_PADAT                0x0000000
 188
 189 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 190 #define CONFIG_SYS_PBDDR                0x0000000
 191 #define CONFIG_SYS_PBDAT                0x0000000
 192
 193 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 194 #define CONFIG_SYS_PCDDR                0x0000000
 195 #define CONFIG_SYS_PCDAT                0x0000000
 196
 197 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 198 #define CONFIG_SYS_PCDDR                0x0000000
 199 #define CONFIG_SYS_PCDAT                0x0000000
 200
 201 #define CONFIG_SYS_PASPAR               0x0F0F
 202 #define CONFIG_SYS_PEHLPAR              0xC0
 203 #define CONFIG_SYS_PUAPAR               0x0F
 204 #define CONFIG_SYS_DDRUA                0x05
 205 #define CONFIG_SYS_PJPAR                0xFF
 206
 207 /*-----------------------------------------------------------------------
 208  * I2C
 209  */
 210
 211 #define CONFIG_SYS_I2C
 212 #define CONFIG_SYS_I2C_FSL
 213
 214 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
 215 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 216
 217 #define CONFIG_SYS_FSL_I2C_SPEED        100000
 218 #define CONFIG_SYS_FSL_I2C_SLAVE        0
 219
 220 #ifdef CONFIG_CMD_DATE
 221 #define CONFIG_RTC_DS1338
 222 #define CONFIG_I2C_RTC_ADDR             0x68
 223 #endif
 224
 225 /*-----------------------------------------------------------------------
 226  * VIDEO configuration
 227  */
 228
 229 #ifdef CONFIG_VIDEO
 230 #define CONFIG_VIDEO_VCXK                       1
 231
 232 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 233 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 234 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS2_BASE
 235
 236 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 237 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 238 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 239
 240 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 241 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 242 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 243
 244 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 245 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 246 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 247
 248 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 249 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 250 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 251
 252 #endif /* CONFIG_VIDEO */
 253 #endif  /* _CONFIG_M5282EVB_H */
 254 /*---------------------------------------------------------------------*/