1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
5 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
8 #ifndef _CONFIG_EB_CPU5282_H_
9 #define _CONFIG_EB_CPU5282_H_
11 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
13 /*----------------------------------------------------------------------*
14 * High Level Configuration Options (easy to change) *
15 *----------------------------------------------------------------------*/
17 #define CONFIG_MCFUART
18 #define CONFIG_SYS_UART_PORT (0)
20 #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
22 #define CONFIG_BOOTCOMMAND "printenv"
24 /*----------------------------------------------------------------------*
26 *----------------------------------------------------------------------*/
28 #define CONFIG_BOOT_RETRY_TIME -1
29 #define CONFIG_RESET_TO_RETRY
31 #define CONFIG_HW_WATCHDOG
33 #define STATUS_LED_ACTIVE 0
35 /*----------------------------------------------------------------------*
36 * Configuration for environment *
37 * Environment is in the second sector of the first 256k of flash *
38 *----------------------------------------------------------------------*/
43 #define CONFIG_BOOTP_BOOTFILESIZE
47 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
48 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
50 #define CONFIG_SYS_LOAD_ADDR 0x20000
52 /*#define CONFIG_SYS_DRAM_TEST 1 */
53 #undef CONFIG_SYS_DRAM_TEST
55 /*----------------------------------------------------------------------*
56 * Clock and PLL Configuration *
57 *----------------------------------------------------------------------*/
58 #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
60 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
62 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
63 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
65 /*----------------------------------------------------------------------*
67 *----------------------------------------------------------------------*/
70 #define CONFIG_MII_INIT 1
71 #define CONFIG_SYS_DISCOVER_PHY
72 #define CONFIG_SYS_RX_ETH_BUFFER 8
73 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
74 #define CONFIG_OVERWRITE_ETHADDR_ONCE
77 /*-------------------------------------------------------------------------
78 * Low Level Configuration Settings
79 * (address mappings, register initial values, etc.)
80 * You should know what you are doing if you make changes here.
81 *-----------------------------------------------------------------------*/
83 #define CONFIG_SYS_MBAR 0x40000000
85 /*-----------------------------------------------------------------------
86 * Definitions for initial stack pointer and data area (in DPRAM)
87 *-----------------------------------------------------------------------*/
89 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
90 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
91 #define CONFIG_SYS_GBL_DATA_OFFSET \
92 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
93 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
95 /*-----------------------------------------------------------------------
96 * Start addresses for the final memory configuration
97 * (Set up by the startup code)
98 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
100 #define CONFIG_SYS_SDRAM_BASE0 0x00000000
101 #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
103 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
104 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
106 #define CONFIG_SYS_MONITOR_LEN 0x20000
107 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
108 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
111 * For booting Linux, the board info and command line data
112 * have to be in the first 8 MB of memory, since this is
113 * the maximum mapped by the Linux kernel during initialization ??
115 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
117 /*-----------------------------------------------------------------------
120 #define CONFIG_FLASH_SHOW_PROGRESS 45
122 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
123 #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
124 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21
126 #define CONFIG_SYS_MAX_FLASH_SECT 128
127 #define CONFIG_SYS_MAX_FLASH_BANKS 1
128 #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
130 #define CONFIG_SYS_FLASH_SIZE 16*1024*1024
131 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
133 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
135 /*-----------------------------------------------------------------------
136 * Cache Configuration
138 #define CONFIG_SYS_CACHELINE_SIZE 16
140 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
141 CONFIG_SYS_INIT_RAM_SIZE - 8)
142 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
143 CONFIG_SYS_INIT_RAM_SIZE - 4)
144 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
145 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
146 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
147 CF_ACR_EN | CF_ACR_SM_ALL)
148 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
149 CF_CACR_CEIB | CF_CACR_DBWE | \
152 /*-----------------------------------------------------------------------
153 * Memory bank definitions
156 #define CONFIG_SYS_CS0_BASE 0xFF000000
157 #define CONFIG_SYS_CS0_CTRL 0x00001980
158 #define CONFIG_SYS_CS0_MASK 0x00FF0001
160 #define CONFIG_SYS_CS2_BASE 0xE0000000
161 #define CONFIG_SYS_CS2_CTRL 0x00001980
162 #define CONFIG_SYS_CS2_MASK 0x000F0001
164 #define CONFIG_SYS_CS3_BASE 0xE0100000
165 #define CONFIG_SYS_CS3_CTRL 0x00001980
166 #define CONFIG_SYS_CS3_MASK 0x000F0001
168 /*-----------------------------------------------------------------------
171 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
172 #define CONFIG_SYS_PADDR 0x0000000
173 #define CONFIG_SYS_PADAT 0x0000000
175 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
176 #define CONFIG_SYS_PBDDR 0x0000000
177 #define CONFIG_SYS_PBDAT 0x0000000
179 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
180 #define CONFIG_SYS_PCDDR 0x0000000
181 #define CONFIG_SYS_PCDAT 0x0000000
183 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
184 #define CONFIG_SYS_PCDDR 0x0000000
185 #define CONFIG_SYS_PCDAT 0x0000000
187 #define CONFIG_SYS_PASPAR 0x0F0F
188 #define CONFIG_SYS_PEHLPAR 0xC0
189 #define CONFIG_SYS_PUAPAR 0x0F
190 #define CONFIG_SYS_DDRUA 0x05
191 #define CONFIG_SYS_PJPAR 0xFF
193 /*-----------------------------------------------------------------------
197 #define CONFIG_SYS_I2C
198 #define CONFIG_SYS_I2C_FSL
200 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
201 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
203 #define CONFIG_SYS_FSL_I2C_SPEED 100000
204 #define CONFIG_SYS_FSL_I2C_SLAVE 0
206 #ifdef CONFIG_CMD_DATE
207 #define CONFIG_RTC_DS1338
208 #define CONFIG_I2C_RTC_ADDR 0x68
211 /*-----------------------------------------------------------------------
212 * VIDEO configuration
216 #define CONFIG_VIDEO_VCXK 1
218 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
219 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
220 #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
222 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
223 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
224 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
226 #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
227 #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
228 #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
230 #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
231 #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
232 #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
234 #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
235 #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
236 #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
238 #endif /* CONFIG_VIDEO */
239 #endif /* _CONFIG_M5282EVB_H */
240 /*---------------------------------------------------------------------*/