include/configs/eb_cpu5282.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   4  *
   5  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   6  */
   7
   8 #ifndef _CONFIG_EB_CPU5282_H_
   9 #define _CONFIG_EB_CPU5282_H_
  10
  11 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  12
  13 /*----------------------------------------------------------------------*
  14  * High Level Configuration Options (easy to change)                    *
  15  *----------------------------------------------------------------------*/
  16
  17 #define CONFIG_SYS_UART_PORT            (0)
  18
  19 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  20
  21 /*----------------------------------------------------------------------*
  22  * Options                                                              *
  23  *----------------------------------------------------------------------*/
  24
  25 #define STATUS_LED_ACTIVE               0
  26
  27 /*----------------------------------------------------------------------*
  28  * Configuration for environment                                        *
  29  * Environment is in the second sector of the first 256k of flash       *
  30  *----------------------------------------------------------------------*/
  31
  32 /*#define CONFIG_SYS_DRAM_TEST          1 */
  33 #undef CONFIG_SYS_DRAM_TEST
  34
  35 /*----------------------------------------------------------------------*
  36  * Clock and PLL Configuration                                          *
  37  *----------------------------------------------------------------------*/
  38 #define CONFIG_SYS_CLK                  80000000      /* 8MHz * 8 */
  39
  40 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  41
  42 #define CONFIG_SYS_MFD          0x02    /* PLL Multiplication Factor Devider */
  43 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
  44
  45 /*----------------------------------------------------------------------*
  46  * Network                                                              *
  47  *----------------------------------------------------------------------*/
  48
  49 #ifdef CONFIG_MCFFEC
  50 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  51 #endif
  52
  53 /*-------------------------------------------------------------------------
  54  * Low Level Configuration Settings
  55  * (address mappings, register initial values, etc.)
  56  * You should know what you are doing if you make changes here.
  57  *-----------------------------------------------------------------------*/
  58
  59 #define CONFIG_SYS_MBAR                 0x40000000
  60
  61 /*-----------------------------------------------------------------------
  62  * Definitions for initial stack pointer and data area (in DPRAM)
  63  *-----------------------------------------------------------------------*/
  64
  65 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  66 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  67
  68 /*-----------------------------------------------------------------------
  69  * Start addresses for the final memory configuration
  70  * (Set up by the startup code)
  71  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  72  */
  73 #define CONFIG_SYS_SDRAM_BASE0          0x00000000
  74 #define CONFIG_SYS_SDRAM_SIZE0          16      /* SDRAM size in MB */
  75
  76 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE0
  77 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE0
  78
  79 #define CONFIG_SYS_MONITOR_LEN          0x20000
  80
  81 /*
  82  * For booting Linux, the board info and command line data
  83  * have to be in the first 8 MB of memory, since this is
  84  * the maximum mapped by the Linux kernel during initialization ??
  85  */
  86 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
  87
  88 /*-----------------------------------------------------------------------
  89  * FLASH organization
  90  */
  91 #define CONFIG_FLASH_SHOW_PROGRESS      45
  92
  93 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
  94 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
  95 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
  96
  97 #define CONFIG_SYS_MAX_FLASH_SECT       128
  98 #define CONFIG_SYS_FLASH_ERASE_TOUT     10000000
  99
 100 #define CONFIG_SYS_FLASH_SIZE           16*1024*1024
 101
 102 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 103
 104 /*-----------------------------------------------------------------------
 105  * Cache Configuration
 106  */
 107
 108 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 109                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 110 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 111                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 112 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 113 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 114                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 115                                          CF_ACR_EN | CF_ACR_SM_ALL)
 116 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 117                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 118                                          CF_CACR_EUSP)
 119
 120 /*-----------------------------------------------------------------------
 121  * Memory bank definitions
 122  */
 123
 124 #define CONFIG_SYS_CS0_BASE             0xFF000000
 125 #define CONFIG_SYS_CS0_CTRL             0x00001980
 126 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 127
 128 #define CONFIG_SYS_CS2_BASE             0xE0000000
 129 #define CONFIG_SYS_CS2_CTRL             0x00001980
 130 #define CONFIG_SYS_CS2_MASK             0x000F0001
 131
 132 #define CONFIG_SYS_CS3_BASE             0xE0100000
 133 #define CONFIG_SYS_CS3_CTRL             0x00001980
 134 #define CONFIG_SYS_CS3_MASK             0x000F0001
 135
 136 /*-----------------------------------------------------------------------
 137  * Port configuration
 138  */
 139 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 140 #define CONFIG_SYS_PADDR                0x0000000
 141 #define CONFIG_SYS_PADAT                0x0000000
 142
 143 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 144 #define CONFIG_SYS_PBDDR                0x0000000
 145 #define CONFIG_SYS_PBDAT                0x0000000
 146
 147 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 148 #define CONFIG_SYS_PCDDR                0x0000000
 149 #define CONFIG_SYS_PCDAT                0x0000000
 150
 151 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 152 #define CONFIG_SYS_PCDDR                0x0000000
 153 #define CONFIG_SYS_PCDAT                0x0000000
 154
 155 #define CONFIG_SYS_PASPAR               0x0F0F
 156 #define CONFIG_SYS_PEHLPAR              0xC0
 157 #define CONFIG_SYS_PUAPAR               0x0F
 158 #define CONFIG_SYS_DDRUA                0x05
 159 #define CONFIG_SYS_PJPAR                0xFF
 160
 161 /*-----------------------------------------------------------------------
 162  * I2C
 163  */
 164
 165 #ifdef CONFIG_CMD_DATE
 166 #define CONFIG_RTC_DS1338
 167 #define CONFIG_I2C_RTC_ADDR             0x68
 168 #endif
 169
 170 /*-----------------------------------------------------------------------
 171  * VIDEO configuration
 172  */
 173
 174 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 175 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 176 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS2_BASE
 177
 178 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 179 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 180 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 181
 182 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 183 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 184 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 185
 186 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 187 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 188 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 189
 190 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 191 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 192 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 193
 194 #endif  /* _CONFIG_M5282EVB_H */
 195 /*---------------------------------------------------------------------*/