1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
5 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
8 #ifndef _CONFIG_EB_CPU5282_H_
9 #define _CONFIG_EB_CPU5282_H_
11 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
13 /*----------------------------------------------------------------------*
14 * High Level Configuration Options (easy to change) *
15 *----------------------------------------------------------------------*/
17 #define CONFIG_SYS_UART_PORT (0)
19 #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
21 /*----------------------------------------------------------------------*
23 *----------------------------------------------------------------------*/
25 #define STATUS_LED_ACTIVE 0
27 /*----------------------------------------------------------------------*
28 * Configuration for environment *
29 * Environment is in the second sector of the first 256k of flash *
30 *----------------------------------------------------------------------*/
34 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
35 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
37 /*#define CONFIG_SYS_DRAM_TEST 1 */
38 #undef CONFIG_SYS_DRAM_TEST
40 /*----------------------------------------------------------------------*
41 * Clock and PLL Configuration *
42 *----------------------------------------------------------------------*/
43 #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
45 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
47 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
48 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
50 /*----------------------------------------------------------------------*
52 *----------------------------------------------------------------------*/
55 #define CONFIG_SYS_DISCOVER_PHY
56 #define CONFIG_OVERWRITE_ETHADDR_ONCE
59 /*-------------------------------------------------------------------------
60 * Low Level Configuration Settings
61 * (address mappings, register initial values, etc.)
62 * You should know what you are doing if you make changes here.
63 *-----------------------------------------------------------------------*/
65 #define CONFIG_SYS_MBAR 0x40000000
67 /*-----------------------------------------------------------------------
68 * Definitions for initial stack pointer and data area (in DPRAM)
69 *-----------------------------------------------------------------------*/
71 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
72 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
73 #define CONFIG_SYS_GBL_DATA_OFFSET \
74 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
75 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
77 /*-----------------------------------------------------------------------
78 * Start addresses for the final memory configuration
79 * (Set up by the startup code)
80 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
82 #define CONFIG_SYS_SDRAM_BASE0 0x00000000
83 #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
85 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
86 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
88 #define CONFIG_SYS_MONITOR_LEN 0x20000
89 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
92 * For booting Linux, the board info and command line data
93 * have to be in the first 8 MB of memory, since this is
94 * the maximum mapped by the Linux kernel during initialization ??
96 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
98 /*-----------------------------------------------------------------------
101 #define CONFIG_FLASH_SHOW_PROGRESS 45
103 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
104 #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
105 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21
107 #define CONFIG_SYS_MAX_FLASH_SECT 128
108 #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
110 #define CONFIG_SYS_FLASH_SIZE 16*1024*1024
111 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
113 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
115 /*-----------------------------------------------------------------------
116 * Cache Configuration
119 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
120 CONFIG_SYS_INIT_RAM_SIZE - 8)
121 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
122 CONFIG_SYS_INIT_RAM_SIZE - 4)
123 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
124 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
125 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
126 CF_ACR_EN | CF_ACR_SM_ALL)
127 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
128 CF_CACR_CEIB | CF_CACR_DBWE | \
131 /*-----------------------------------------------------------------------
132 * Memory bank definitions
135 #define CONFIG_SYS_CS0_BASE 0xFF000000
136 #define CONFIG_SYS_CS0_CTRL 0x00001980
137 #define CONFIG_SYS_CS0_MASK 0x00FF0001
139 #define CONFIG_SYS_CS2_BASE 0xE0000000
140 #define CONFIG_SYS_CS2_CTRL 0x00001980
141 #define CONFIG_SYS_CS2_MASK 0x000F0001
143 #define CONFIG_SYS_CS3_BASE 0xE0100000
144 #define CONFIG_SYS_CS3_CTRL 0x00001980
145 #define CONFIG_SYS_CS3_MASK 0x000F0001
147 /*-----------------------------------------------------------------------
150 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
151 #define CONFIG_SYS_PADDR 0x0000000
152 #define CONFIG_SYS_PADAT 0x0000000
154 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
155 #define CONFIG_SYS_PBDDR 0x0000000
156 #define CONFIG_SYS_PBDAT 0x0000000
158 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
159 #define CONFIG_SYS_PCDDR 0x0000000
160 #define CONFIG_SYS_PCDAT 0x0000000
162 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
163 #define CONFIG_SYS_PCDDR 0x0000000
164 #define CONFIG_SYS_PCDAT 0x0000000
166 #define CONFIG_SYS_PASPAR 0x0F0F
167 #define CONFIG_SYS_PEHLPAR 0xC0
168 #define CONFIG_SYS_PUAPAR 0x0F
169 #define CONFIG_SYS_DDRUA 0x05
170 #define CONFIG_SYS_PJPAR 0xFF
172 /*-----------------------------------------------------------------------
176 #ifdef CONFIG_CMD_DATE
177 #define CONFIG_RTC_DS1338
178 #define CONFIG_I2C_RTC_ADDR 0x68
181 /*-----------------------------------------------------------------------
182 * VIDEO configuration
185 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
186 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
187 #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
189 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
190 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
191 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
193 #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
194 #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
195 #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
197 #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
198 #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
199 #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
201 #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
202 #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
203 #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
205 #endif /* _CONFIG_M5282EVB_H */
206 /*---------------------------------------------------------------------*/