include/configs/eb_cpu5282.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   4  *
   5  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   6  */
   7
   8 #ifndef _CONFIG_EB_CPU5282_H_
   9 #define _CONFIG_EB_CPU5282_H_
  10
  11 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  12
  13 /*----------------------------------------------------------------------*
  14  * High Level Configuration Options (easy to change)                    *
  15  *----------------------------------------------------------------------*/
  16
  17 #define CONFIG_SYS_UART_PORT            (0)
  18
  19 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  20
  21 /*----------------------------------------------------------------------*
  22  * Options                                                              *
  23  *----------------------------------------------------------------------*/
  24
  25 #define STATUS_LED_ACTIVE               0
  26
  27 /*----------------------------------------------------------------------*
  28  * Configuration for environment                                        *
  29  * Environment is in the second sector of the first 256k of flash       *
  30  *----------------------------------------------------------------------*/
  31
  32 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size      */
  33 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  34
  35 /*#define CONFIG_SYS_DRAM_TEST          1 */
  36 #undef CONFIG_SYS_DRAM_TEST
  37
  38 /*----------------------------------------------------------------------*
  39  * Clock and PLL Configuration                                          *
  40  *----------------------------------------------------------------------*/
  41 #define CONFIG_SYS_CLK                  80000000      /* 8MHz * 8 */
  42
  43 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  44
  45 #define CONFIG_SYS_MFD          0x02    /* PLL Multiplication Factor Devider */
  46 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
  47
  48 /*----------------------------------------------------------------------*
  49  * Network                                                              *
  50  *----------------------------------------------------------------------*/
  51
  52 #ifdef CONFIG_MCFFEC
  53 #define CONFIG_SYS_DISCOVER_PHY
  54 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  55 #endif
  56
  57 /*-------------------------------------------------------------------------
  58  * Low Level Configuration Settings
  59  * (address mappings, register initial values, etc.)
  60  * You should know what you are doing if you make changes here.
  61  *-----------------------------------------------------------------------*/
  62
  63 #define CONFIG_SYS_MBAR                 0x40000000
  64
  65 /*-----------------------------------------------------------------------
  66  * Definitions for initial stack pointer and data area (in DPRAM)
  67  *-----------------------------------------------------------------------*/
  68
  69 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  70 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  71 #define CONFIG_SYS_GBL_DATA_OFFSET      \
  72         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  73 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  74
  75 /*-----------------------------------------------------------------------
  76  * Start addresses for the final memory configuration
  77  * (Set up by the startup code)
  78  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  79  */
  80 #define CONFIG_SYS_SDRAM_BASE0          0x00000000
  81 #define CONFIG_SYS_SDRAM_SIZE0          16      /* SDRAM size in MB */
  82
  83 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE0
  84 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE0
  85
  86 #define CONFIG_SYS_MONITOR_LEN          0x20000
  87 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
  88
  89 /*
  90  * For booting Linux, the board info and command line data
  91  * have to be in the first 8 MB of memory, since this is
  92  * the maximum mapped by the Linux kernel during initialization ??
  93  */
  94 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
  95
  96 /*-----------------------------------------------------------------------
  97  * FLASH organization
  98  */
  99 #define CONFIG_FLASH_SHOW_PROGRESS      45
 100
 101 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 102 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
 103 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 104
 105 #define CONFIG_SYS_MAX_FLASH_SECT       128
 106 #define CONFIG_SYS_FLASH_ERASE_TOUT     10000000
 107
 108 #define CONFIG_SYS_FLASH_SIZE           16*1024*1024
 109 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 110
 111 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 112
 113 /*-----------------------------------------------------------------------
 114  * Cache Configuration
 115  */
 116
 117 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 118                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 119 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 120                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 121 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 122 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 123                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 124                                          CF_ACR_EN | CF_ACR_SM_ALL)
 125 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 126                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 127                                          CF_CACR_EUSP)
 128
 129 /*-----------------------------------------------------------------------
 130  * Memory bank definitions
 131  */
 132
 133 #define CONFIG_SYS_CS0_BASE             0xFF000000
 134 #define CONFIG_SYS_CS0_CTRL             0x00001980
 135 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 136
 137 #define CONFIG_SYS_CS2_BASE             0xE0000000
 138 #define CONFIG_SYS_CS2_CTRL             0x00001980
 139 #define CONFIG_SYS_CS2_MASK             0x000F0001
 140
 141 #define CONFIG_SYS_CS3_BASE             0xE0100000
 142 #define CONFIG_SYS_CS3_CTRL             0x00001980
 143 #define CONFIG_SYS_CS3_MASK             0x000F0001
 144
 145 /*-----------------------------------------------------------------------
 146  * Port configuration
 147  */
 148 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 149 #define CONFIG_SYS_PADDR                0x0000000
 150 #define CONFIG_SYS_PADAT                0x0000000
 151
 152 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 153 #define CONFIG_SYS_PBDDR                0x0000000
 154 #define CONFIG_SYS_PBDAT                0x0000000
 155
 156 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 157 #define CONFIG_SYS_PCDDR                0x0000000
 158 #define CONFIG_SYS_PCDAT                0x0000000
 159
 160 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 161 #define CONFIG_SYS_PCDDR                0x0000000
 162 #define CONFIG_SYS_PCDAT                0x0000000
 163
 164 #define CONFIG_SYS_PASPAR               0x0F0F
 165 #define CONFIG_SYS_PEHLPAR              0xC0
 166 #define CONFIG_SYS_PUAPAR               0x0F
 167 #define CONFIG_SYS_DDRUA                0x05
 168 #define CONFIG_SYS_PJPAR                0xFF
 169
 170 /*-----------------------------------------------------------------------
 171  * I2C
 172  */
 173
 174 #ifdef CONFIG_CMD_DATE
 175 #define CONFIG_RTC_DS1338
 176 #define CONFIG_I2C_RTC_ADDR             0x68
 177 #endif
 178
 179 /*-----------------------------------------------------------------------
 180  * VIDEO configuration
 181  */
 182
 183 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 184 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 185 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS2_BASE
 186
 187 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 188 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 189 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 190
 191 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 192 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 193 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 194
 195 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 196 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 197 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 198
 199 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 200 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 201 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 202
 203 #endif  /* _CONFIG_M5282EVB_H */
 204 /*---------------------------------------------------------------------*/