include/configs/eNET.h

   1 /*
   2  * (C) Copyright 2008
   3  * Graeme Russ, graeme.russ@gmail.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <asm/ibmpc.h>
  25 /*
  26  * board/config.h - configuration options, board specific
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36 #define CONFIG_SYS_SC520
  37 #define CONFIG_SYS_SC520_SSI
  38 #define CONFIG_SHOW_BOOT_PROGRESS
  39 #define CONFIG_LAST_STAGE_INIT
  40
  41 /*-----------------------------------------------------------------------
  42  * Watchdog Configuration
  43  * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
  44  * bottom (processor) board MUST be removed!
  45  */
  46 #undef CONFIG_WATCHDOG
  47 #define CONFIG_HW_WATCHDOG
  48
  49 /*-----------------------------------------------------------------------
  50  * Real Time Clock Configuration
  51  */
  52 #define CONFIG_RTC_MC146818
  53 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS          0
  54
  55 /*-----------------------------------------------------------------------
  56  * Serial Configuration
  57  */
  58 #define CONFIG_SERIAL_MULTI
  59 #define CONFIG_CONS_INDEX                       1
  60 #define CONFIG_SYS_NS16550
  61 #define CONFIG_SYS_NS16550_SERIAL
  62 #define CONFIG_SYS_NS16550_REG_SIZE             1
  63 #define CONFIG_SYS_NS16550_CLK                  1843200
  64 #define CONFIG_BAUDRATE                         9600
  65 #define CONFIG_SYS_BAUDRATE_TABLE               {300, 600, 1200, 2400, 4800, \
  66                                                  9600, 19200, 38400, 115200}
  67 #define CONFIG_SYS_NS16550_COM1                 UART0_BASE
  68 #define CONFIG_SYS_NS16550_COM2                 UART1_BASE
  69 #define CONFIG_SYS_NS16550_COM3                 (0x1000 + UART0_BASE)
  70 #define CONFIG_SYS_NS16550_COM4                 (0x1000 + UART1_BASE)
  71 #define CONFIG_SYS_NS16550_PORT_MAPPED
  72
  73 /*-----------------------------------------------------------------------
  74  * Video Configuration
  75  */
  76 #undef CONFIG_VIDEO
  77 #undef CONFIG_CFB_CONSOLE
  78
  79 /*-----------------------------------------------------------------------
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84 #define CONFIG_CMD_BDI
  85 #define CONFIG_CMD_BOOTD
  86 #define CONFIG_CMD_CONSOLE
  87 #define CONFIG_CMD_DATE
  88 #define CONFIG_CMD_ECHO
  89 #define CONFIG_CMD_FLASH
  90 #define CONFIG_CMD_FPGA
  91 #define CONFIG_CMD_IMI
  92 #define CONFIG_CMD_IMLS
  93 #define CONFIG_CMD_IRQ
  94 #define CONFIG_CMD_ITEST
  95 #define CONFIG_CMD_LOADB
  96 #define CONFIG_CMD_LOADS
  97 #define CONFIG_CMD_MEMORY
  98 #define CONFIG_CMD_MISC
  99 #define CONFIG_CMD_NET
 100 #undef CONFIG_CMD_NFS
 101 #define CONFIG_CMD_PCI
 102 #define CONFIG_CMD_PING
 103 #define CONFIG_CMD_RUN
 104 #define CONFIG_CMD_SAVEENV
 105 #define CONFIG_CMD_SETGETDCR
 106 #define CONFIG_CMD_SOURCE
 107 #define CONFIG_CMD_XIMG
 108
 109 #define CONFIG_BOOTDELAY                        15
 110 #define CONFIG_BOOTARGS                         "root=/dev/mtdblock0 console=ttyS0,9600"
 111
 112 #if defined(CONFIG_CMD_KGDB)
 113 #define CONFIG_KGDB_BAUDRATE                    115200
 114 #define CONFIG_KGDB_SER_INDEX                   2
 115 #endif
 116
 117 /*
 118  * Miscellaneous configurable options
 119  */
 120 #define CONFIG_SYS_LONGHELP
 121 #define CONFIG_SYS_PROMPT                       "boot > "
 122 #define CONFIG_SYS_CBSIZE                       256
 123 #define CONFIG_SYS_PBSIZE                       (CONFIG_SYS_CBSIZE + \
 124                                                  sizeof(CONFIG_SYS_PROMPT) + \
 125                                                  16)
 126 #define CONFIG_SYS_MAXARGS                      16
 127 #define CONFIG_SYS_BARGSIZE                     CONFIG_SYS_CBSIZE
 128
 129 #define CONFIG_SYS_MEMTEST_START                0x00100000
 130 #define CONFIG_SYS_MEMTEST_END                  0x01000000
 131 #define CONFIG_SYS_LOAD_ADDR                    0x100000
 132 #define CONFIG_SYS_HZ                           1000
 133
 134 /*-----------------------------------------------------------------------
 135  * SDRAM Configuration
 136  */
 137 #define CONFIG_SYS_SDRAM_DRCTMCTL               0x18
 138 #define CONFIG_SYS_SDRAM_REFRESH_RATE           156
 139 #define CONFIG_NR_DRAM_BANKS                    4
 140
 141 /* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
 142 #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
 143 #undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
 144 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
 145 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
 146
 147 /*-----------------------------------------------------------------------
 148  * CPU Features
 149  */
 150 #define CONFIG_SYS_SC520_HIGH_SPEED             0
 151 #define CONFIG_SYS_SC520_RESET
 152 #define CONFIG_SYS_SC520_TIMER
 153 #undef  CONFIG_SYS_GENERIC_TIMER
 154 #define CONFIG_SYS_PCAT_INTERRUPTS
 155 #define CONFIG_SYS_NUM_IRQS                     16
 156
 157 /*-----------------------------------------------------------------------
 158  * Memory organization:
 159  * 32kB Stack
 160  * 16kB Cache-As-RAM @ 0x19200000
 161  * 256kB Monitor
 162  * (128kB + Environment Sector Size) malloc pool
 163  */
 164 #define CONFIG_SYS_STACK_SIZE                   (32 * 1024)
 165 #define CONFIG_SYS_CAR_ADDR                     0x19200000
 166 #define CONFIG_SYS_CAR_SIZE                     (16 * 1024)
 167 #define CONFIG_SYS_INIT_SP_ADDR                 (CONFIG_SYS_CAR_ADDR + \
 168                                                  CONFIG_SYS_CAR_SIZE)
 169 #define CONFIG_SYS_MONITOR_BASE                 CONFIG_SYS_TEXT_BASE
 170 #define CONFIG_SYS_MONITOR_LEN                  (256 * 1024)
 171 #define CONFIG_SYS_MALLOC_LEN                   (CONFIG_ENV_SECT_SIZE + \
 172                                                  128*1024)
 173 /* Address of temporary Global Data */
 174 #define CONFIG_SYS_INIT_GD_ADDR                 CONFIG_SYS_CAR_ADDR
 175
 176
 177 /* allow to overwrite serial and ethaddr */
 178 #define CONFIG_ENV_OVERWRITE
 179
 180 /*-----------------------------------------------------------------------
 181  * FLASH configuration
 182  * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
 183  * 16MB StrataFlash #1 @ 0x10000000
 184  * 16MB StrataFlash #2 @ 0x11000000
 185  */
 186 #define CONFIG_FLASH_CFI_DRIVER
 187 #define CONFIG_FLASH_CFI_LEGACY
 188 #define CONFIG_SYS_FLASH_CFI
 189 #define CONFIG_SYS_MAX_FLASH_BANKS              3
 190 #define CONFIG_SYS_FLASH_BASE                   0x38000000
 191 #define CONFIG_SYS_FLASH_BASE_1                 0x10000000
 192 #define CONFIG_SYS_FLASH_BASE_2                 0x11000000
 193 #define CONFIG_SYS_FLASH_BANKS_LIST             {CONFIG_SYS_FLASH_BASE,   \
 194                                                  CONFIG_SYS_FLASH_BASE_1, \
 195                                                  CONFIG_SYS_FLASH_BASE_2}
 196 #define CONFIG_SYS_FLASH_EMPTY_INFO
 197 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 198 #define CONFIG_SYS_MAX_FLASH_SECT               128
 199 #define CONFIG_SYS_FLASH_CFI_WIDTH              FLASH_CFI_8BIT
 200 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
 201 #define CONFIG_SYS_FLASH_ERASE_TOUT             2000    /* ms */
 202 #define CONFIG_SYS_FLASH_WRITE_TOUT             2000    /* ms */
 203
 204 /*-----------------------------------------------------------------------
 205  * Environment configuration
 206  * - Boot flash is 512kB with 64kB sectors
 207  * - StrataFlash is 32MB with 128kB sectors
 208  * - Redundant embedded environment is 25% of the Boot flash
 209  * - Redundant StrataFlash environment is <1% of the StrataFlash
 210  * - Environment is therefore located in StrataFlash
 211  * - Primary copy is located in first sector of first flash
 212  * - Redundant copy is located in second sector of first flash
 213  * - Stack is only 32kB, so environment size is limited to 4kB
 214  */
 215 #define CONFIG_ENV_IS_IN_FLASH
 216 #define CONFIG_ENV_SECT_SIZE                    0x20000
 217 #define CONFIG_ENV_SIZE                         0x01000
 218 #define CONFIG_ENV_ADDR                         CONFIG_SYS_FLASH_BASE_1
 219 #define CONFIG_ENV_ADDR_REDUND                  (CONFIG_SYS_FLASH_BASE_1 + \
 220                                                  CONFIG_ENV_SECT_SIZE)
 221 #define CONFIG_ENV_SIZE_REDUND                  CONFIG_ENV_SIZE
 222
 223 /*-----------------------------------------------------------------------
 224  * PCI configuration
 225  */
 226 #define CONFIG_PCI
 227 #define CONFIG_PCI_PNP
 228 #define CONFIG_SYS_FIRST_PCI_IRQ                10
 229 #define CONFIG_SYS_SECOND_PCI_IRQ               9
 230 #define CONFIG_SYS_THIRD_PCI_IRQ                11
 231 #define CONFIG_SYS_FORTH_PCI_IRQ                15
 232
 233 /*-----------------------------------------------------------------------
 234  * Network device (TRL8100B) support
 235  */
 236 #define CONFIG_RTL8139
 237
 238 /*-----------------------------------------------------------------------
 239  * BOOTCS Control (for AM29LV040B-120JC)
 240  *
 241  * 000 0 00 0 000 11 0 011 }- 0x0033
 242  * \ / | \| | \ / \| | \ /
 243  *  |  |  | |  |   | |  |
 244  *  |  |  | |  |   | |  +---- 3 Wait States (First Access)
 245  *  |  |  | |  |   | +------- Reserved
 246  *  |  |  | |  |   +--------- 3 Wait States (Subsequent Access)
 247  *  |  |  | |  +------------- Reserved
 248  *  |  |  | +---------------- Non-Paged Mode
 249  *  |  |  +------------------ 8 Bit Wide
 250  *  |  +--------------------- GP Bus
 251  *  +------------------------ Reserved
 252  */
 253 #define CONFIG_SYS_SC520_BOOTCS_CTRL            0x0033
 254
 255 /*-----------------------------------------------------------------------
 256  * ROMCS Control (for E28F128J3A-150 StrataFlash)
 257  *
 258  * 000 0 01 1 000 01 0 101 }- 0x0615
 259  * \ / | \| | \ / \| | \ /
 260  *  |  |  | |  |   | |  |
 261  *  |  |  | |  |   | |  +---- 5 Wait States (First Access)
 262  *  |  |  | |  |   | +------- Reserved
 263  *  |  |  | |  |   +--------- 1 Wait State (Subsequent Access)
 264  *  |  |  | |  +------------- Reserved
 265  *  |  |  | +---------------- Paged Mode
 266  *  |  |  +------------------ 16 Bit Wide
 267  *  |  +--------------------- GP Bus
 268  *  +------------------------ Reserved
 269  */
 270 #define CONFIG_SYS_SC520_ROMCS1_CTRL            0x0615
 271 #define CONFIG_SYS_SC520_ROMCS2_CTRL            0x0615
 272
 273 /*-----------------------------------------------------------------------
 274  * SC520 General Purpose Bus configuration
 275  *
 276  * Chip Select Offset           1 Clock Cycle
 277  * Chip Select Pulse Width      8 Clock Cycles
 278  * Chip Select Read Offset      2 Clock Cycles
 279  * Chip Select Read Width       6 Clock Cycles
 280  * Chip Select Write Offset     2 Clock Cycles
 281  * Chip Select Write Width      6 Clock Cycles
 282  * Chip Select Recovery Time    2 Clock Cycles
 283  *
 284  * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
 285  *
 286  *   |<-------------General Purpose Bus Cycle---------------->|
 287  *   |                                                        |
 288  * ----------------------\__________________/------------------
 289  *   |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
 290  *
 291  * ------------------------\_______________/-------------------
 292  *   |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
 293  *
 294  * --------------------------\_______________/-----------------
 295  *   |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
 296  *
 297  * ________/-----------\_______________________________________
 298  *   |<--->|<--------->|
 299  *      ^         ^
 300  * (GPALEOFF + 1) |
 301  *                |
 302  *         (GPALEW + 1)
 303  */
 304 #define CONFIG_SYS_SC520_GPCSOFF                0x00
 305 #define CONFIG_SYS_SC520_GPCSPW                 0x07
 306 #define CONFIG_SYS_SC520_GPRDOFF                0x01
 307 #define CONFIG_SYS_SC520_GPRDW                  0x05
 308 #define CONFIG_SYS_SC520_GPWROFF                0x01
 309 #define CONFIG_SYS_SC520_GPWRW                  0x05
 310 #define CONFIG_SYS_SC520_GPCSRT                 0x01
 311
 312 /*-----------------------------------------------------------------------
 313  * SC520 Programmable I/O configuration
 314  *
 315  * Pin    Mode          Dir.    Description
 316  * ----------------------------------------------------------------------
 317  * PIO0   PIO           Output  Unused
 318  * PIO1   GPBHE#        Output  GP Bus Byte High Enable (active low)
 319  * PIO2   PIO           Output  Auxiliary power output enable
 320  * PIO3   GPAEN         Output  GP Bus Address Enable
 321  * PIO4   PIO           Output  Top Board Enable (active low)
 322  * PIO5   PIO           Output  StrataFlash 16 bit mode (low = 8 bit mode)
 323  * PIO6   PIO           Input   Data output of Power Supply ADC
 324  * PIO7   PIO           Output  Clock input to Power Supply ADC
 325  * PIO8   PIO           Output  Chip Select input of Power Supply ADC
 326  * PIO9   PIO           Output  StrataFlash 1 Reset / Power Down (active low)
 327  * PIO10  PIO           Output  StrataFlash 2 Reset / Power Down (active low)
 328  * PIO11  PIO           Input   StrataFlash 1 Status
 329  * PIO12  PIO           Input   StrataFlash 2 Status
 330  * PIO13  GPIRQ10#      Input   Can Bus / I2C IRQ (active low)
 331  * PIO14  PIO           Input   Low Input Voltage Warning (active low)
 332  * PIO15  PIO           Output  Watchdog (must toggle at least every 1.6s)
 333  * PIO16  PIO           Input   Power Fail
 334  * PIO17  GPIRQ6        Input   Compact Flash 1 IRQ (active low)
 335  * PIO18  GPIRQ5        Input   Compact Flash 2 IRQ (active low)
 336  * PIO19  GPIRQ4#       Input   Dual-Port RAM IRQ (active low)
 337  * PIO20  GPIRQ3        Input   UART D IRQ
 338  * PIO21  GPIRQ2        Input   UART C IRQ
 339  * PIO22  GPIRQ1        Input   UART B IRQ
 340  * PIO23  GPIRQ0        Input   UART A IRQ
 341  * PIO24  GPDBUFOE#     Output  GP Bus Data Bus Buffer Output Enable
 342  * PIO25  PIO           Input   Battery OK Indication
 343  * PIO26  GPMEMCS16#    Input   GP Bus Memory Chip-Select 16-bit access
 344  * PIO27  GPCS0#        Output  SRAM 1 Chip Select
 345  * PIO28  PIO           Input   Top Board UART CTS
 346  * PIO29  PIO           Output  FPGA Program Mode (active low)
 347  * PIO30  PIO           Input   FPGA Initialised (active low)
 348  * PIO31  PIO           Input   FPGA Done (active low)
 349  */
 350 #define CONFIG_SYS_SC520_PIOPFS15_0             0x200a
 351 #define CONFIG_SYS_SC520_PIOPFS31_16            0x0dfe
 352 #define CONFIG_SYS_SC520_PIODIR15_0             0x87bf
 353 #define CONFIG_SYS_SC520_PIODIR31_16            0x2900
 354
 355 /*-----------------------------------------------------------------------
 356  * PIO Pin defines
 357  */
 358 #define CONFIG_SYS_ENET_AUX_PWR                 0x0004
 359 #define CONFIG_SYS_ENET_TOP_BRD_PWR             0x0010
 360 #define CONFIG_SYS_ENET_SF_WIDTH                0x0020
 361 #define CONFIG_SYS_ENET_PWR_ADC_DATA            0x0040
 362 #define CONFIG_SYS_ENET_PWR_ADC_CLK             0x0080
 363 #define CONFIG_SYS_ENET_PWR_ADC_CS              0x0100
 364 #define CONFIG_SYS_ENET_SF1_MODE                0x0200
 365 #define CONFIG_SYS_ENET_SF2_MODE                0x0400
 366 #define CONFIG_SYS_ENET_SF1_STATUS              0x0800
 367 #define CONFIG_SYS_ENET_SF2_STATUS              0x1000
 368 #define CONFIG_SYS_ENET_PWR_STATUS              0x4000
 369 #define CONFIG_SYS_ENET_WATCHDOG                0x8000
 370
 371 #define CONFIG_SYS_ENET_PWR_FAIL                0x0001
 372 #define CONFIG_SYS_ENET_BAT_OK                  0x0200
 373 #define CONFIG_SYS_ENET_TOP_BRD_CTS             0x1000
 374 #define CONFIG_SYS_ENET_FPGA_PROG               0x2000
 375 #define CONFIG_SYS_ENET_FPGA_INIT               0x4000
 376 #define CONFIG_SYS_ENET_FPGA_DONE               0x8000
 377
 378 /*-----------------------------------------------------------------------
 379  * Chip Select Pin Function Select
 380  *
 381  * 1 1 1 1 1 0 0 0 }- 0xf8
 382  * | | | | | | | |
 383  * | | | | | | | +--- Reserved
 384  * | | | | | | +----- GPCS1_SEL = ROMCS1#
 385  * | | | | | +------- GPCS2_SEL = ROMCS2#
 386  * | | | | +--------- GPCS3_SEL = GPCS3
 387  * | | | +----------- GPCS4_SEL = GPCS4
 388  * | | +------------- GPCS5_SEL = GPCS5
 389  * | +--------------- GPCS6_SEL = GPCS6
 390  * +----------------- GPCS7_SEL = GPCS7
 391  */
 392 #define CONFIG_SYS_SC520_CSPFS                  0xf8
 393
 394 /*-----------------------------------------------------------------------
 395  * Clock Select (CLKTIMER[CLKTEST] pin)
 396  *
 397  * 0 111 00 1 0 }- 0x72
 398  * | \ / \| | |
 399  * |  |   | | +--- Pin Disabled
 400  * |  |   | +----- Pin is an output
 401  * |  |   +------- Reserved
 402  * |  +----------- Disabled (pin stays Low)
 403  * +-------------- Reserved
 404  */
 405 #define CONFIG_SYS_SC520_CLKSEL                 0x72
 406
 407 /*-----------------------------------------------------------------------
 408  * Address Decode Control
 409  *
 410  * 0 00 0 0 0 0 0 }- 0x00
 411  * | \| | | | | |
 412  * |  | | | | | +--- Integrated UART 1 is enabled
 413  * |  | | | | +----- Integrated UART 2 is enabled
 414  * |  | | | +------- Integrated RTC is enabled
 415  * |  | | +--------- Reserved
 416  * |  | +----------- I/O Hole accesses are forwarded to the external GP bus
 417  * |  +------------- Reserved
 418  * +---------------- Write-protect violations do not generate an IRQ
 419  */
 420 #define CONFIG_SYS_SC520_ADDDECCTL              0x00
 421
 422 /*-----------------------------------------------------------------------
 423  * UART Control
 424  *
 425  * 00000 1 1 1 }- 0x07
 426  * \___/ | | |
 427  *   |   | | +--- Transmit TC interrupt enable
 428  *   |   | +----- Receive TC interrupt enable
 429  *   |   +------- 1.8432 MHz
 430  *   +----------- Reserved
 431  */
 432 #define CONFIG_SYS_SC520_UART1CTL               0x07
 433 #define CONFIG_SYS_SC520_UART2CTL               0x07
 434
 435 /*-----------------------------------------------------------------------
 436  * System Arbiter Control
 437  *
 438  * 00000 1 1 0 }- 0x06
 439  * \___/ | | |
 440  *   |   | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
 441  *   |   | +----- The system arbiter operates in concurrent mode
 442  *   |   +------- Park the PCI bus on the last master that acquired the bus
 443  *   +----------- Reserved
 444  */
 445 #define CONFIG_SYS_SC520_SYSARBCTL              0x06
 446
 447 /*-----------------------------------------------------------------------
 448  * System Arbiter Master Enable
 449  *
 450  * 00000000000 0 0 0 1 1 }- 0x06
 451  * \_________/ | | | | |
 452  *      |      | | | | +--- PCI master REQ0 enabled (Ethernet 1)
 453  *      |      | | | +----- PCI master REQ1 enabled (Ethernet 2)
 454  *      |      | | +------- PCI master REQ2 disabled
 455  *      |      | +--------- PCI master REQ3 disabled
 456  *      |      +----------- PCI master REQ4 disabled
 457  *      +------------------ Reserved
 458  */
 459 #define CONFIG_SYS_SC520_SYSARBMENB             0x0003
 460
 461 /*-----------------------------------------------------------------------
 462  * System Arbiter Master Enable
 463  *
 464  * 0 0000 0 00 0000 1 000 }- 0x06
 465  * | \__/ | \| \__/ | \_/
 466  * |   |  |  |   |  |  +---- Reserved
 467  * |   |  |  |   |  +------- Enable CPU-to-PCI bus write posting
 468  * |   |  |  |   +---------- Reserved
 469  * |   |  |  +-------------- PCI bus reads to SDRAM are not automatically
 470  * |   |  |                  retried
 471  * |   |  +----------------- Target read FIFOs are not snooped during write
 472  * |   |                     transactions
 473  * |   +-------------------- Reserved
 474  * +------------------------ Deassert the PCI bus reset signal
 475  */
 476 #define CONFIG_SYS_SC520_HBCTL                  0x08
 477
 478 /*-----------------------------------------------------------------------
 479  * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
 480  * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
 481  * \ / | | | | \----+----/ \-----+------/
 482  *  |  | | | |      |            +---------- Start at 0x38000000
 483  *  |  | | | |      +----------------------- 512kB Region Size
 484  *  |  | | | |                               ((7 + 1) * 64kB)
 485  *  |  | | | +------------------------------ 64kB Page Size
 486  *  |  | | +-------------------------------- Writes Enabled (So it can be
 487  *  |  | |                                   reprogrammed!)
 488  *  |  | +---------------------------------- Caching Disabled
 489  *  |  +------------------------------------ Execution Enabled
 490  *  +--------------------------------------- BOOTCS
 491  */
 492 #define CONFIG_SYS_SC520_BOOTCS_PAR             0x8a01f800
 493
 494 /*-----------------------------------------------------------------------
 495  * Cache-As-RAM (Targets Boot Flash)
 496  *
 497  * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
 498  * \ / | | | | \--+--/ \-------+--------/
 499  *  |  | | | |    |            +------------ Start at 0x19200000
 500  *  |  | | | |    +------------------------- 64k Region Size
 501  *  |  | | | |                               ((15 + 1) * 4kB)
 502  *  |  | | | +------------------------------ 4kB Page Size
 503  *  |  | | +-------------------------------- Writes Enabled
 504  *  |  | +---------------------------------- Caching Enabled
 505  *  |  +------------------------------------ Execution Prevented
 506  *  +--------------------------------------- BOOTCS
 507  */
 508 #define CONFIG_SYS_SC520_CAR_PAR                0x903d9200
 509
 510 /*-----------------------------------------------------------------------
 511  * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
 512  *
 513  * 001 110 0 000100000 0001000000000000 }- 0x38201000
 514  * \ / \ / | \---+---/ \------+-------/
 515  *  |   |  |     |            +----------- Start at 0x00001000
 516  *  |   |  |     +------------------------ 33 Bytes (0x20 + 1)
 517  *  |   |  +------------------------------ Ignored
 518  *  |   +--------------------------------- GPCS6
 519  *  +------------------------------------- GP Bus I/O
 520  */
 521 #define CONFIG_SYS_SC520_LLIO_PAR               0x38201000
 522
 523 /*-----------------------------------------------------------------------
 524  * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
 525  * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
 526  *
 527  * 010 101 0 0000000 100000000000000000 }- 0x54020000
 528  * 010 111 0 0000000 100000000000000001 }- 0x5c020001
 529  * \ / \ / | \--+--/ \-------+--------/
 530  *  |   |  |    |            +------------ Start at 0x200000000
 531  *  |   |  |    |                                   0x200010000
 532  *  |   |  |    +------------------------- 4kB Region Size
 533  *  |   |  |                               ((0 + 1) * 4kB)
 534  *  |   |  +------------------------------ 4k Page Size
 535  *  |   +--------------------------------- GPCS5
 536  *  |                                      GPCS7
 537  *  +------------------------------------- GP Bus Memory
 538  */
 539 #define CONFIG_SYS_SC520_CF1_PAR                0x54020000
 540 #define CONFIG_SYS_SC520_CF2_PAR                0x5c020001
 541
 542 /*-----------------------------------------------------------------------
 543  * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
 544  * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
 545  * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
 546  * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
 547  *
 548  * 001 000 0 000000111 0001001111111000 }- 0x200713f8
 549  * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
 550  * 001 011 0 000000111 0001001011111000 }- 0x300711f8
 551  * 001 011 0 000000111 0001001011111000 }- 0x340710f8
 552  * \ / \ / | \---+---/ \------+-------/
 553  *  |   |  |     |            +----------- Start at 0x013f8
 554  *  |   |  |     |                                  0x012f8
 555  *  |   |  |     |                                  0x011f8
 556  *  |   |  |     |                                  0x010f8
 557  *  |   |  |     +------------------------ 33 Bytes (32 + 1)
 558  *  |   |  +------------------------------ Ignored
 559  *  |   +--------------------------------- GPCS6
 560  *  +------------------------------------- GP Bus I/O
 561  */
 562 #define CONFIG_SYS_SC520_UARTA_PAR              0x200713f8
 563 #define CONFIG_SYS_SC520_UARTB_PAR              0x2c0712f8
 564 #define CONFIG_SYS_SC520_UARTC_PAR              0x300711f8
 565 #define CONFIG_SYS_SC520_UARTD_PAR              0x340710f8
 566
 567 /*-----------------------------------------------------------------------
 568  * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
 569  * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
 570  *
 571  * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
 572  * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
 573  * \ / | | | | \----+----/ \-----+------/
 574  *  |  | | | |      |            +---------- Start at 0x10000000
 575  *  |  | | | |      |                                 0x11000000
 576  *  |  | | | |      +----------------------- 16MB Region Size
 577  *  |  | | | |                               ((255 + 1) * 64kB)
 578  *  |  | | | +------------------------------ 64kB Page Size
 579  *  |  | | +-------------------------------- Writes Enabled
 580  *  |  | +---------------------------------- Caching Disabled
 581  *  |  +------------------------------------ Execution Enabled
 582  *  +--------------------------------------- ROMCS1
 583  *                                           ROMCS2
 584  */
 585 #define CONFIG_SYS_SC520_SF1_PAR                0xaa3fd000
 586 #define CONFIG_SYS_SC520_SF2_PAR                0xca3fd100
 587
 588 /*-----------------------------------------------------------------------
 589  * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
 590  * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
 591  *
 592  * 010 000 1 00000001111 01100100000000 }- 0x4203d900
 593  * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
 594  * \ / \ / | \----+----/ \-----+------/
 595  *  |   |  |      |            +---------- Start at 0x19000000
 596  *  |   |  |      |                                 0x19100000
 597  *  |   |  |      +----------------------- 1MB Region Size
 598  *  |   |  |                               ((15 + 1) * 64kB)
 599  *  |   |  +------------------------------ 64kB Page Size
 600  *  |   +--------------------------------- GPCS0
 601  *  |                                      GPCS3
 602  *  +------------------------------------- GP Bus Memory
 603  */
 604 #define CONFIG_SYS_SC520_SRAM1_PAR              0x4203d900
 605 #define CONFIG_SYS_SC520_SRAM2_PAR              0x4e03d910
 606
 607 /*-----------------------------------------------------------------------
 608  * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
 609  *
 610  * 010 100 0 00000000 11000000100000000 }- 0x50018100
 611  * \ / \ / | \---+--/ \-------+-------/
 612  *  |   |  |     |            +----------- Start at 0x18100000
 613  *  |   |  |     +------------------------ 4kB Region Size
 614  *  |   |  |                               ((0 + 1) * 4kB)
 615  *  |   |  +------------------------------ 4kB Page Size
 616  *  |   +--------------------------------- GPCS4
 617  *  +------------------------------------- GP Bus Memory
 618  */
 619 #define CONFIG_SYS_SC520_DPRAM_PAR              0x50018100
 620
 621 #endif  /* __CONFIG_H */