include/configs/eNET.h

   1 /*
   2  * (C) Copyright 2008
   3  * Graeme Russ, graeme.russ@gmail.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <asm/ibmpc.h>
  25 /*
  26  * board/config.h - configuration options, board specific
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36 #define CONFIG_SYS_SC520
  37 #define CONFIG_SYS_SC520_SSI
  38 #define CONFIG_SHOW_BOOT_PROGRESS
  39 #define CONFIG_LAST_STAGE_INIT
  40
  41 /*-----------------------------------------------------------------------
  42  * Watchdog Configuration
  43  * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
  44  * bottom (processor) board MUST be removed!
  45  */
  46 #undef CONFIG_WATCHDOG
  47 #define CONFIG_HW_WATCHDOG
  48
  49 /*-----------------------------------------------------------------------
  50  * Real Time Clock Configuration
  51  */
  52 #define CONFIG_RTC_MC146818
  53 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS          0
  54
  55 /*-----------------------------------------------------------------------
  56  * Serial Configuration
  57  */
  58 #define CONFIG_CONS_INDEX                       1
  59 #define CONFIG_SYS_NS16550
  60 #define CONFIG_SYS_NS16550_SERIAL
  61 #define CONFIG_SYS_NS16550_REG_SIZE             1
  62 #define CONFIG_SYS_NS16550_CLK                  1843200
  63 #define CONFIG_BAUDRATE                         9600
  64 #define CONFIG_SYS_BAUDRATE_TABLE               {300, 600, 1200, 2400, 4800, \
  65                                                  9600, 19200, 38400, 115200}
  66 #define CONFIG_SYS_NS16550_COM1                 UART0_BASE
  67 #define CONFIG_SYS_NS16550_COM2                 UART1_BASE
  68 #define CONFIG_SYS_NS16550_COM3                 (0x1000 + UART0_BASE)
  69 #define CONFIG_SYS_NS16550_COM4                 (0x1000 + UART1_BASE)
  70 #define CONFIG_SYS_NS16550_PORT_MAPPED
  71
  72 /*-----------------------------------------------------------------------
  73  * Video Configuration
  74  */
  75 #undef CONFIG_VIDEO
  76 #undef CONFIG_CFB_CONSOLE
  77
  78 /*-----------------------------------------------------------------------
  79  * Command line configuration.
  80  */
  81 #include <config_cmd_default.h>
  82
  83 #define CONFIG_CMD_BDI
  84 #define CONFIG_CMD_BOOTD
  85 #define CONFIG_CMD_CONSOLE
  86 #define CONFIG_CMD_DATE
  87 #define CONFIG_CMD_ECHO
  88 #define CONFIG_CMD_FLASH
  89 #define CONFIG_CMD_FPGA
  90 #define CONFIG_CMD_IMI
  91 #define CONFIG_CMD_IMLS
  92 #define CONFIG_CMD_IRQ
  93 #define CONFIG_CMD_ITEST
  94 #define CONFIG_CMD_LOADB
  95 #define CONFIG_CMD_LOADS
  96 #define CONFIG_CMD_MEMORY
  97 #define CONFIG_CMD_MISC
  98 #define CONFIG_CMD_NET
  99 #undef CONFIG_CMD_NFS
 100 #define CONFIG_CMD_PCI
 101 #define CONFIG_CMD_PING
 102 #define CONFIG_CMD_RUN
 103 #define CONFIG_CMD_SAVEENV
 104 #define CONFIG_CMD_SETGETDCR
 105 #define CONFIG_CMD_SOURCE
 106 #define CONFIG_CMD_XIMG
 107 #define CONFIG_CMD_ZBOOT
 108
 109 #define CONFIG_BOOTDELAY                        15
 110 #define CONFIG_BOOTARGS                         "root=/dev/mtdblock0 console=ttyS0,9600"
 111
 112 #if defined(CONFIG_CMD_KGDB)
 113 #define CONFIG_KGDB_BAUDRATE                    115200
 114 #define CONFIG_KGDB_SER_INDEX                   2
 115 #endif
 116
 117 /*
 118  * Miscellaneous configurable options
 119  */
 120 #define CONFIG_SYS_LONGHELP
 121 #define CONFIG_SYS_PROMPT                       "boot > "
 122 #define CONFIG_SYS_CBSIZE                       256
 123 #define CONFIG_SYS_PBSIZE                       (CONFIG_SYS_CBSIZE + \
 124                                                  sizeof(CONFIG_SYS_PROMPT) + \
 125                                                  16)
 126 #define CONFIG_SYS_MAXARGS                      16
 127 #define CONFIG_SYS_BARGSIZE                     CONFIG_SYS_CBSIZE
 128
 129 #define CONFIG_SYS_MEMTEST_START                0x00100000
 130 #define CONFIG_SYS_MEMTEST_END                  0x01000000
 131 #define CONFIG_SYS_LOAD_ADDR                    0x100000
 132 #define CONFIG_SYS_HZ                           1000
 133
 134 /*-----------------------------------------------------------------------
 135  * SDRAM Configuration
 136  */
 137 #define CONFIG_SYS_SDRAM_DRCTMCTL               0x18
 138 #define CONFIG_SYS_SDRAM_REFRESH_RATE           156
 139 #define CONFIG_NR_DRAM_BANKS                    4
 140
 141 /* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
 142 #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
 143 #undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
 144 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
 145 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
 146
 147 /*-----------------------------------------------------------------------
 148  * CPU Features
 149  */
 150 #define CONFIG_SYS_SC520_HIGH_SPEED             0
 151 #define CONFIG_SYS_SC520_RESET
 152 #define CONFIG_SYS_SC520_TIMER
 153 #undef  CONFIG_SYS_GENERIC_TIMER
 154 #define CONFIG_SYS_PCAT_INTERRUPTS
 155 #define CONFIG_SYS_NUM_IRQS                     16
 156 #define CONFIG_SYS_PC_BIOS
 157 #define CONFIG_SYS_PCI_BIOS
 158 #define CONFIG_SYS_X86_REALMODE
 159 #define CONFIG_SYS_X86_ISR_TIMER
 160
 161 /*-----------------------------------------------------------------------
 162  * Memory organization:
 163  * 32kB Stack
 164  * 16kB Cache-As-RAM @ 0x19200000
 165  * 256kB Monitor
 166  * (128kB + Environment Sector Size) malloc pool
 167  */
 168 #define CONFIG_SYS_STACK_SIZE                   (32 * 1024)
 169 #define CONFIG_SYS_CAR_ADDR                     0x19200000
 170 #define CONFIG_SYS_CAR_SIZE                     (16 * 1024)
 171 #define CONFIG_SYS_INIT_SP_ADDR                 (CONFIG_SYS_CAR_ADDR + \
 172                                                  CONFIG_SYS_CAR_SIZE)
 173 #define CONFIG_SYS_MONITOR_BASE                 CONFIG_SYS_TEXT_BASE
 174 #define CONFIG_SYS_MONITOR_LEN                  (256 * 1024)
 175 #define CONFIG_SYS_MALLOC_LEN                   (CONFIG_ENV_SECT_SIZE + \
 176                                                  128*1024)
 177 /* Address of temporary Global Data */
 178 #define CONFIG_SYS_INIT_GD_ADDR                 CONFIG_SYS_CAR_ADDR
 179
 180
 181 /* allow to overwrite serial and ethaddr */
 182 #define CONFIG_ENV_OVERWRITE
 183
 184 /*-----------------------------------------------------------------------
 185  * FLASH configuration
 186  * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
 187  * 16MB StrataFlash #1 @ 0x10000000
 188  * 16MB StrataFlash #2 @ 0x11000000
 189  */
 190 #define CONFIG_FLASH_CFI_DRIVER
 191 #define CONFIG_FLASH_CFI_LEGACY
 192 #define CONFIG_SYS_FLASH_CFI
 193 #define CONFIG_SYS_MAX_FLASH_BANKS              3
 194 #define CONFIG_SYS_FLASH_BASE                   0x38000000
 195 #define CONFIG_SYS_FLASH_BASE_1                 0x10000000
 196 #define CONFIG_SYS_FLASH_BASE_2                 0x11000000
 197 #define CONFIG_SYS_FLASH_BANKS_LIST             {CONFIG_SYS_FLASH_BASE,   \
 198                                                  CONFIG_SYS_FLASH_BASE_1, \
 199                                                  CONFIG_SYS_FLASH_BASE_2}
 200 #define CONFIG_SYS_FLASH_EMPTY_INFO
 201 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 202 #define CONFIG_SYS_MAX_FLASH_SECT               128
 203 #define CONFIG_SYS_FLASH_CFI_WIDTH              FLASH_CFI_8BIT
 204 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
 205 #define CONFIG_SYS_FLASH_ERASE_TOUT             2000    /* ms */
 206 #define CONFIG_SYS_FLASH_WRITE_TOUT             2000    /* ms */
 207
 208 /*-----------------------------------------------------------------------
 209  * Environment configuration
 210  * - Boot flash is 512kB with 64kB sectors
 211  * - StrataFlash is 32MB with 128kB sectors
 212  * - Redundant embedded environment is 25% of the Boot flash
 213  * - Redundant StrataFlash environment is <1% of the StrataFlash
 214  * - Environment is therefore located in StrataFlash
 215  * - Primary copy is located in first sector of first flash
 216  * - Redundant copy is located in second sector of first flash
 217  * - Stack is only 32kB, so environment size is limited to 4kB
 218  */
 219 #define CONFIG_ENV_IS_IN_FLASH
 220 #define CONFIG_ENV_SECT_SIZE                    0x20000
 221 #define CONFIG_ENV_SIZE                         0x01000
 222 #define CONFIG_ENV_ADDR                         CONFIG_SYS_FLASH_BASE_1
 223 #define CONFIG_ENV_ADDR_REDUND                  (CONFIG_SYS_FLASH_BASE_1 + \
 224                                                  CONFIG_ENV_SECT_SIZE)
 225 #define CONFIG_ENV_SIZE_REDUND                  CONFIG_ENV_SIZE
 226
 227 /*-----------------------------------------------------------------------
 228  * PCI configuration
 229  */
 230 #define CONFIG_PCI
 231 #define CONFIG_PCI_PNP
 232 #define CONFIG_SYS_FIRST_PCI_IRQ                10
 233 #define CONFIG_SYS_SECOND_PCI_IRQ               9
 234 #define CONFIG_SYS_THIRD_PCI_IRQ                11
 235 #define CONFIG_SYS_FORTH_PCI_IRQ                15
 236
 237 /*-----------------------------------------------------------------------
 238  * Network device (TRL8100B) support
 239  */
 240 #define CONFIG_RTL8139
 241
 242 /*-----------------------------------------------------------------------
 243  * BOOTCS Control (for AM29LV040B-120JC)
 244  *
 245  * 000 0 00 0 000 11 0 011 }- 0x0033
 246  * \ / | \| | \ / \| | \ /
 247  *  |  |  | |  |   | |  |
 248  *  |  |  | |  |   | |  +---- 3 Wait States (First Access)
 249  *  |  |  | |  |   | +------- Reserved
 250  *  |  |  | |  |   +--------- 3 Wait States (Subsequent Access)
 251  *  |  |  | |  +------------- Reserved
 252  *  |  |  | +---------------- Non-Paged Mode
 253  *  |  |  +------------------ 8 Bit Wide
 254  *  |  +--------------------- GP Bus
 255  *  +------------------------ Reserved
 256  */
 257 #define CONFIG_SYS_SC520_BOOTCS_CTRL            0x0033
 258
 259 /*-----------------------------------------------------------------------
 260  * ROMCS Control (for E28F128J3A-150 StrataFlash)
 261  *
 262  * 000 0 01 1 000 01 0 101 }- 0x0615
 263  * \ / | \| | \ / \| | \ /
 264  *  |  |  | |  |   | |  |
 265  *  |  |  | |  |   | |  +---- 5 Wait States (First Access)
 266  *  |  |  | |  |   | +------- Reserved
 267  *  |  |  | |  |   +--------- 1 Wait State (Subsequent Access)
 268  *  |  |  | |  +------------- Reserved
 269  *  |  |  | +---------------- Paged Mode
 270  *  |  |  +------------------ 16 Bit Wide
 271  *  |  +--------------------- GP Bus
 272  *  +------------------------ Reserved
 273  */
 274 #define CONFIG_SYS_SC520_ROMCS1_CTRL            0x0615
 275 #define CONFIG_SYS_SC520_ROMCS2_CTRL            0x0615
 276
 277 /*-----------------------------------------------------------------------
 278  * SC520 General Purpose Bus configuration
 279  *
 280  * Chip Select Offset           1 Clock Cycle
 281  * Chip Select Pulse Width      8 Clock Cycles
 282  * Chip Select Read Offset      2 Clock Cycles
 283  * Chip Select Read Width       6 Clock Cycles
 284  * Chip Select Write Offset     2 Clock Cycles
 285  * Chip Select Write Width      6 Clock Cycles
 286  * Chip Select Recovery Time    2 Clock Cycles
 287  *
 288  * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
 289  *
 290  *   |<-------------General Purpose Bus Cycle---------------->|
 291  *   |                                                        |
 292  * ----------------------\__________________/------------------
 293  *   |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
 294  *
 295  * ------------------------\_______________/-------------------
 296  *   |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
 297  *
 298  * --------------------------\_______________/-----------------
 299  *   |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
 300  *
 301  * ________/-----------\_______________________________________
 302  *   |<--->|<--------->|
 303  *      ^         ^
 304  * (GPALEOFF + 1) |
 305  *                |
 306  *         (GPALEW + 1)
 307  */
 308 #define CONFIG_SYS_SC520_GPCSOFF                0x00
 309 #define CONFIG_SYS_SC520_GPCSPW                 0x07
 310 #define CONFIG_SYS_SC520_GPRDOFF                0x01
 311 #define CONFIG_SYS_SC520_GPRDW                  0x05
 312 #define CONFIG_SYS_SC520_GPWROFF                0x01
 313 #define CONFIG_SYS_SC520_GPWRW                  0x05
 314 #define CONFIG_SYS_SC520_GPCSRT                 0x01
 315
 316 /*-----------------------------------------------------------------------
 317  * SC520 Programmable I/O configuration
 318  *
 319  * Pin    Mode          Dir.    Description
 320  * ----------------------------------------------------------------------
 321  * PIO0   PIO           Output  Unused
 322  * PIO1   GPBHE#        Output  GP Bus Byte High Enable (active low)
 323  * PIO2   PIO           Output  Auxiliary power output enable
 324  * PIO3   GPAEN         Output  GP Bus Address Enable
 325  * PIO4   PIO           Output  Top Board Enable (active low)
 326  * PIO5   PIO           Output  StrataFlash 16 bit mode (low = 8 bit mode)
 327  * PIO6   PIO           Input   Data output of Power Supply ADC
 328  * PIO7   PIO           Output  Clock input to Power Supply ADC
 329  * PIO8   PIO           Output  Chip Select input of Power Supply ADC
 330  * PIO9   PIO           Output  StrataFlash 1 Reset / Power Down (active low)
 331  * PIO10  PIO           Output  StrataFlash 2 Reset / Power Down (active low)
 332  * PIO11  PIO           Input   StrataFlash 1 Status
 333  * PIO12  PIO           Input   StrataFlash 2 Status
 334  * PIO13  GPIRQ10#      Input   Can Bus / I2C IRQ (active low)
 335  * PIO14  PIO           Input   Low Input Voltage Warning (active low)
 336  * PIO15  PIO           Output  Watchdog (must toggle at least every 1.6s)
 337  * PIO16  PIO           Input   Power Fail
 338  * PIO17  GPIRQ6        Input   Compact Flash 1 IRQ (active low)
 339  * PIO18  GPIRQ5        Input   Compact Flash 2 IRQ (active low)
 340  * PIO19  GPIRQ4#       Input   Dual-Port RAM IRQ (active low)
 341  * PIO20  GPIRQ3        Input   UART D IRQ
 342  * PIO21  GPIRQ2        Input   UART C IRQ
 343  * PIO22  GPIRQ1        Input   UART B IRQ
 344  * PIO23  GPIRQ0        Input   UART A IRQ
 345  * PIO24  GPDBUFOE#     Output  GP Bus Data Bus Buffer Output Enable
 346  * PIO25  PIO           Input   Battery OK Indication
 347  * PIO26  GPMEMCS16#    Input   GP Bus Memory Chip-Select 16-bit access
 348  * PIO27  GPCS0#        Output  SRAM 1 Chip Select
 349  * PIO28  PIO           Input   Top Board UART CTS
 350  * PIO29  PIO           Output  FPGA Program Mode (active low)
 351  * PIO30  PIO           Input   FPGA Initialised (active low)
 352  * PIO31  PIO           Input   FPGA Done (active low)
 353  */
 354 #define CONFIG_SYS_SC520_PIOPFS15_0             0x200a
 355 #define CONFIG_SYS_SC520_PIOPFS31_16            0x0dfe
 356 #define CONFIG_SYS_SC520_PIODIR15_0             0x87bf
 357 #define CONFIG_SYS_SC520_PIODIR31_16            0x2900
 358
 359 /*-----------------------------------------------------------------------
 360  * PIO Pin defines
 361  */
 362 #define CONFIG_SYS_ENET_AUX_PWR                 0x0004
 363 #define CONFIG_SYS_ENET_TOP_BRD_PWR             0x0010
 364 #define CONFIG_SYS_ENET_SF_WIDTH                0x0020
 365 #define CONFIG_SYS_ENET_PWR_ADC_DATA            0x0040
 366 #define CONFIG_SYS_ENET_PWR_ADC_CLK             0x0080
 367 #define CONFIG_SYS_ENET_PWR_ADC_CS              0x0100
 368 #define CONFIG_SYS_ENET_SF1_MODE                0x0200
 369 #define CONFIG_SYS_ENET_SF2_MODE                0x0400
 370 #define CONFIG_SYS_ENET_SF1_STATUS              0x0800
 371 #define CONFIG_SYS_ENET_SF2_STATUS              0x1000
 372 #define CONFIG_SYS_ENET_PWR_STATUS              0x4000
 373 #define CONFIG_SYS_ENET_WATCHDOG                0x8000
 374
 375 #define CONFIG_SYS_ENET_PWR_FAIL                0x0001
 376 #define CONFIG_SYS_ENET_BAT_OK                  0x0200
 377 #define CONFIG_SYS_ENET_TOP_BRD_CTS             0x1000
 378 #define CONFIG_SYS_ENET_FPGA_PROG               0x2000
 379 #define CONFIG_SYS_ENET_FPGA_INIT               0x4000
 380 #define CONFIG_SYS_ENET_FPGA_DONE               0x8000
 381
 382 /*-----------------------------------------------------------------------
 383  * Chip Select Pin Function Select
 384  *
 385  * 1 1 1 1 1 0 0 0 }- 0xf8
 386  * | | | | | | | |
 387  * | | | | | | | +--- Reserved
 388  * | | | | | | +----- GPCS1_SEL = ROMCS1#
 389  * | | | | | +------- GPCS2_SEL = ROMCS2#
 390  * | | | | +--------- GPCS3_SEL = GPCS3
 391  * | | | +----------- GPCS4_SEL = GPCS4
 392  * | | +------------- GPCS5_SEL = GPCS5
 393  * | +--------------- GPCS6_SEL = GPCS6
 394  * +----------------- GPCS7_SEL = GPCS7
 395  */
 396 #define CONFIG_SYS_SC520_CSPFS                  0xf8
 397
 398 /*-----------------------------------------------------------------------
 399  * Clock Select (CLKTIMER[CLKTEST] pin)
 400  *
 401  * 0 111 00 1 0 }- 0x72
 402  * | \ / \| | |
 403  * |  |   | | +--- Pin Disabled
 404  * |  |   | +----- Pin is an output
 405  * |  |   +------- Reserved
 406  * |  +----------- Disabled (pin stays Low)
 407  * +-------------- Reserved
 408  */
 409 #define CONFIG_SYS_SC520_CLKSEL                 0x72
 410
 411 /*-----------------------------------------------------------------------
 412  * Address Decode Control
 413  *
 414  * 0 00 0 0 0 0 0 }- 0x00
 415  * | \| | | | | |
 416  * |  | | | | | +--- Integrated UART 1 is enabled
 417  * |  | | | | +----- Integrated UART 2 is enabled
 418  * |  | | | +------- Integrated RTC is enabled
 419  * |  | | +--------- Reserved
 420  * |  | +----------- I/O Hole accesses are forwarded to the external GP bus
 421  * |  +------------- Reserved
 422  * +---------------- Write-protect violations do not generate an IRQ
 423  */
 424 #define CONFIG_SYS_SC520_ADDDECCTL              0x00
 425
 426 /*-----------------------------------------------------------------------
 427  * UART Control
 428  *
 429  * 00000 1 1 1 }- 0x07
 430  * \___/ | | |
 431  *   |   | | +--- Transmit TC interrupt enable
 432  *   |   | +----- Receive TC interrupt enable
 433  *   |   +------- 1.8432 MHz
 434  *   +----------- Reserved
 435  */
 436 #define CONFIG_SYS_SC520_UART1CTL               0x07
 437 #define CONFIG_SYS_SC520_UART2CTL               0x07
 438
 439 /*-----------------------------------------------------------------------
 440  * System Arbiter Control
 441  *
 442  * 00000 1 1 0 }- 0x06
 443  * \___/ | | |
 444  *   |   | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
 445  *   |   | +----- The system arbiter operates in concurrent mode
 446  *   |   +------- Park the PCI bus on the last master that acquired the bus
 447  *   +----------- Reserved
 448  */
 449 #define CONFIG_SYS_SC520_SYSARBCTL              0x06
 450
 451 /*-----------------------------------------------------------------------
 452  * System Arbiter Master Enable
 453  *
 454  * 00000000000 0 0 0 1 1 }- 0x06
 455  * \_________/ | | | | |
 456  *      |      | | | | +--- PCI master REQ0 enabled (Ethernet 1)
 457  *      |      | | | +----- PCI master REQ1 enabled (Ethernet 2)
 458  *      |      | | +------- PCI master REQ2 disabled
 459  *      |      | +--------- PCI master REQ3 disabled
 460  *      |      +----------- PCI master REQ4 disabled
 461  *      +------------------ Reserved
 462  */
 463 #define CONFIG_SYS_SC520_SYSARBMENB             0x0003
 464
 465 /*-----------------------------------------------------------------------
 466  * System Arbiter Master Enable
 467  *
 468  * 0 0000 0 00 0000 1 000 }- 0x06
 469  * | \__/ | \| \__/ | \_/
 470  * |   |  |  |   |  |  +---- Reserved
 471  * |   |  |  |   |  +------- Enable CPU-to-PCI bus write posting
 472  * |   |  |  |   +---------- Reserved
 473  * |   |  |  +-------------- PCI bus reads to SDRAM are not automatically
 474  * |   |  |                  retried
 475  * |   |  +----------------- Target read FIFOs are not snooped during write
 476  * |   |                     transactions
 477  * |   +-------------------- Reserved
 478  * +------------------------ Deassert the PCI bus reset signal
 479  */
 480 #define CONFIG_SYS_SC520_HBCTL                  0x08
 481
 482 /*-----------------------------------------------------------------------
 483  * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
 484  * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
 485  * \ / | | | | \----+----/ \-----+------/
 486  *  |  | | | |      |            +---------- Start at 0x38000000
 487  *  |  | | | |      +----------------------- 512kB Region Size
 488  *  |  | | | |                               ((7 + 1) * 64kB)
 489  *  |  | | | +------------------------------ 64kB Page Size
 490  *  |  | | +-------------------------------- Writes Enabled (So it can be
 491  *  |  | |                                   reprogrammed!)
 492  *  |  | +---------------------------------- Caching Disabled
 493  *  |  +------------------------------------ Execution Enabled
 494  *  +--------------------------------------- BOOTCS
 495  */
 496 #define CONFIG_SYS_SC520_BOOTCS_PAR             0x8a01f800
 497
 498 /*-----------------------------------------------------------------------
 499  * Cache-As-RAM (Targets Boot Flash)
 500  *
 501  * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
 502  * \ / | | | | \--+--/ \-------+--------/
 503  *  |  | | | |    |            +------------ Start at 0x19200000
 504  *  |  | | | |    +------------------------- 64k Region Size
 505  *  |  | | | |                               ((15 + 1) * 4kB)
 506  *  |  | | | +------------------------------ 4kB Page Size
 507  *  |  | | +-------------------------------- Writes Enabled
 508  *  |  | +---------------------------------- Caching Enabled
 509  *  |  +------------------------------------ Execution Prevented
 510  *  +--------------------------------------- BOOTCS
 511  */
 512 #define CONFIG_SYS_SC520_CAR_PAR                0x903d9200
 513
 514 /*-----------------------------------------------------------------------
 515  * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
 516  *
 517  * 001 110 0 000100000 0001000000000000 }- 0x38201000
 518  * \ / \ / | \---+---/ \------+-------/
 519  *  |   |  |     |            +----------- Start at 0x00001000
 520  *  |   |  |     +------------------------ 33 Bytes (0x20 + 1)
 521  *  |   |  +------------------------------ Ignored
 522  *  |   +--------------------------------- GPCS6
 523  *  +------------------------------------- GP Bus I/O
 524  */
 525 #define CONFIG_SYS_SC520_LLIO_PAR               0x38201000
 526
 527 /*-----------------------------------------------------------------------
 528  * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
 529  * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
 530  *
 531  * 010 101 0 0000000 100000000000000000 }- 0x54020000
 532  * 010 111 0 0000000 100000000000000001 }- 0x5c020001
 533  * \ / \ / | \--+--/ \-------+--------/
 534  *  |   |  |    |            +------------ Start at 0x200000000
 535  *  |   |  |    |                                   0x200010000
 536  *  |   |  |    +------------------------- 4kB Region Size
 537  *  |   |  |                               ((0 + 1) * 4kB)
 538  *  |   |  +------------------------------ 4k Page Size
 539  *  |   +--------------------------------- GPCS5
 540  *  |                                      GPCS7
 541  *  +------------------------------------- GP Bus Memory
 542  */
 543 #define CONFIG_SYS_SC520_CF1_PAR                0x54020000
 544 #define CONFIG_SYS_SC520_CF2_PAR                0x5c020001
 545
 546 /*-----------------------------------------------------------------------
 547  * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
 548  * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
 549  * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
 550  * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
 551  *
 552  * 001 000 0 000000111 0001001111111000 }- 0x200713f8
 553  * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
 554  * 001 011 0 000000111 0001001011111000 }- 0x300711f8
 555  * 001 011 0 000000111 0001001011111000 }- 0x340710f8
 556  * \ / \ / | \---+---/ \------+-------/
 557  *  |   |  |     |            +----------- Start at 0x013f8
 558  *  |   |  |     |                                  0x012f8
 559  *  |   |  |     |                                  0x011f8
 560  *  |   |  |     |                                  0x010f8
 561  *  |   |  |     +------------------------ 33 Bytes (32 + 1)
 562  *  |   |  +------------------------------ Ignored
 563  *  |   +--------------------------------- GPCS6
 564  *  +------------------------------------- GP Bus I/O
 565  */
 566 #define CONFIG_SYS_SC520_UARTA_PAR              0x200713f8
 567 #define CONFIG_SYS_SC520_UARTB_PAR              0x2c0712f8
 568 #define CONFIG_SYS_SC520_UARTC_PAR              0x300711f8
 569 #define CONFIG_SYS_SC520_UARTD_PAR              0x340710f8
 570
 571 /*-----------------------------------------------------------------------
 572  * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
 573  * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
 574  *
 575  * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
 576  * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
 577  * \ / | | | | \----+----/ \-----+------/
 578  *  |  | | | |      |            +---------- Start at 0x10000000
 579  *  |  | | | |      |                                 0x11000000
 580  *  |  | | | |      +----------------------- 16MB Region Size
 581  *  |  | | | |                               ((255 + 1) * 64kB)
 582  *  |  | | | +------------------------------ 64kB Page Size
 583  *  |  | | +-------------------------------- Writes Enabled
 584  *  |  | +---------------------------------- Caching Disabled
 585  *  |  +------------------------------------ Execution Enabled
 586  *  +--------------------------------------- ROMCS1
 587  *                                           ROMCS2
 588  */
 589 #define CONFIG_SYS_SC520_SF1_PAR                0xaa3fd000
 590 #define CONFIG_SYS_SC520_SF2_PAR                0xca3fd100
 591
 592 /*-----------------------------------------------------------------------
 593  * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
 594  * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
 595  *
 596  * 010 000 1 00000001111 01100100000000 }- 0x4203d900
 597  * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
 598  * \ / \ / | \----+----/ \-----+------/
 599  *  |   |  |      |            +---------- Start at 0x19000000
 600  *  |   |  |      |                                 0x19100000
 601  *  |   |  |      +----------------------- 1MB Region Size
 602  *  |   |  |                               ((15 + 1) * 64kB)
 603  *  |   |  +------------------------------ 64kB Page Size
 604  *  |   +--------------------------------- GPCS0
 605  *  |                                      GPCS3
 606  *  +------------------------------------- GP Bus Memory
 607  */
 608 #define CONFIG_SYS_SC520_SRAM1_PAR              0x4203d900
 609 #define CONFIG_SYS_SC520_SRAM2_PAR              0x4e03d910
 610
 611 /*-----------------------------------------------------------------------
 612  * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
 613  *
 614  * 010 100 0 00000000 11000000100000000 }- 0x50018100
 615  * \ / \ / | \---+--/ \-------+-------/
 616  *  |   |  |     |            +----------- Start at 0x18100000
 617  *  |   |  |     +------------------------ 4kB Region Size
 618  *  |   |  |                               ((0 + 1) * 4kB)
 619  *  |   |  +------------------------------ 4kB Page Size
 620  *  |   +--------------------------------- GPCS4
 621  *  +------------------------------------- GP Bus Memory
 622  */
 623 #define CONFIG_SYS_SC520_DPRAM_PAR              0x50018100
 624
 625 #endif  /* __CONFIG_H */