include/configs/eNET.h

   1 /*
   2  * (C) Copyright 2008
   3  * Graeme Russ, graeme.russ@gmail.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * Stuff still to be dealt with -
  33  */
  34 #define CONFIG_RTC_MC146818
  35
  36 /*
  37  * High Level Configuration Options
  38  * (easy to change)
  39  */
  40 #define DEBUG_PARSER
  41
  42 #define CONFIG_X86                      1       /* Intel X86 CPU */
  43 #define CONFIG_SYS_SC520                1       /* AMD SC520 */
  44 #define CONFIG_SYS_SC520_SSI
  45 #define CONFIG_SHOW_BOOT_PROGRESS       1
  46 #define CONFIG_LAST_STAGE_INIT          1
  47
  48 /*
  49  * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
  50  * bottom (processor) board MUST be removed!
  51  */
  52 #undef CONFIG_WATCHDOG
  53 #undef CONFIG_HW_WATCHDOG
  54
  55  /*-----------------------------------------------------------------------
  56   * Video Configuration
  57   */
  58 #undef CONFIG_VIDEO                     /* No Video Hardware */
  59 #undef CONFIG_CFB_CONSOLE
  60
  61 /*
  62  * Size of malloc() pool
  63  */
  64 #define CONFIG_MALLOC_SIZE      (CONFIG_SYS_ENV_SIZE + 128*1024)
  65
  66 #define CONFIG_BAUDRATE         9600
  67
  68 /*-----------------------------------------------------------------------
  69  * Command line configuration.
  70  */
  71 #include <config_cmd_default.h>
  72
  73 #define CONFIG_CMD_AUTOSCRIPT   /* Autoscript Support           */
  74 #define CONFIG_CMD_BDI          /* bdinfo                       */
  75 #define CONFIG_CMD_BOOTD        /* bootd                        */
  76 #define CONFIG_CMD_CONSOLE      /* coninfo                      */
  77 #define CONFIG_CMD_ECHO         /* echo arguments               */
  78 #define CONFIG_CMD_SAVEENV      /* saveenv                      */
  79 #define CONFIG_CMD_FLASH        /* flinfo, erase, protect       */
  80 #define CONFIG_CMD_FPGA         /* FPGA configuration Support   */
  81 #define CONFIG_CMD_IMI          /* iminfo                       */
  82 #define CONFIG_CMD_IMLS         /* List all found images        */
  83 #define CONFIG_CMD_ITEST        /* Integer (and string) test    */
  84 #define CONFIG_CMD_LOADB        /* loadb                        */
  85 #define CONFIG_CMD_LOADS        /* loads                        */
  86 #define CONFIG_CMD_MEMORY       /* md mm nm mw cp cmp crc base loop mtest */
  87 #define CONFIG_CMD_MISC         /* Misc functions like sleep etc*/
  88 #undef CONFIG_CMD_NET           /* bootp, tftpboot, rarpboot    */
  89 #undef CONFIG_CMD_NFS           /* NFS support                  */
  90 #define CONFIG_CMD_RUN          /* run command in env variable  */
  91 #define CONFIG_CMD_SETGETDCR    /* DCR support on 4xx           */
  92 #define CONFIG_CMD_XIMG         /* Load part of Multi Image     */
  93 #undef CONFIG_CMD_IRQ           /* IRQ Information              */
  94
  95 #define CONFIG_BOOTDELAY                15
  96 #define CONFIG_BOOTARGS                 "root=/dev/mtdblock0 console=ttyS0,9600"
  97 /* #define CONFIG_BOOTCOMMAND           "bootm 38000000" */
  98
  99 #if defined(CONFIG_CMD_KGDB)
 100 #define CONFIG_KGDB_BAUDRATE            115200          /* speed to run kgdb serial port */
 101 #define CONFIG_KGDB_SER_INDEX           2               /* which serial port to use */
 102 #endif
 103
 104 /*
 105  * Miscellaneous configurable options
 106  */
 107 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 108 #define CONFIG_SYS_PROMPT               "boot > "       /* Monitor Command Prompt       */
 109 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 110 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 111                                          sizeof(CONFIG_SYS_PROMPT) + \
 112                                          16)            /* Print Buffer Size */
 113 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 114 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 115
 116 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 117 #define CONFIG_SYS_MEMTEST_END          0x01000000      /* 1 ... 16 MB in DRAM  */
 118
 119 #undef  CONFIG_SYS_CLKS_IN_HZ           /* everything, incl board info, in Hz */
 120
 121 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 122
 123 #define CONFIG_SYS_HZ                   1024            /* incrementer freq: 1kHz */
 124
 125                                                 /* valid baudrates */
 126 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 127
 128 /*-----------------------------------------------------------------------
 129  * SDRAM Configuration
 130  */
 131 #define CONFIG_SYS_SDRAM_DRCTMCTL       0x18
 132 #define CONFIG_NR_DRAM_BANKS            4
 133
 134 /* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
 135 #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
 136 #undef CONFIG_SYS_SDRAM_REFRESH_RATE
 137 #undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
 138 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
 139 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
 140
 141 /*-----------------------------------------------------------------------
 142  * CPU Features
 143  */
 144 #define CONFIG_SYS_SC520_HIGH_SPEED     0       /* 100 or 133MHz */
 145 #undef  CONFIG_SYS_SC520_RESET                  /* use SC520 MMCR's to reset cpu */
 146 #define CONFIG_SYS_SC520_TIMER                  /* use SC520 swtimers */
 147 #undef  CONFIG_SYS_GENERIC_TIMER                /* use the i8254 PIT timers */
 148 #undef  CONFIG_SYS_TSC_TIMER                    /* use the Pentium TSC timers */
 149 #define CONFIG_SYS_USE_SIO_UART         0       /* prefer the uarts on the SIO to those
 150                                          * in the SC520 on the CDP */
 151
 152 /*-----------------------------------------------------------------------
 153  * Memory organization
 154  */
 155 #define CONFIG_SYS_STACK_SIZE           0x8000          /* Size of bootloader stack */
 156 #define CONFIG_SYS_BL_START_FLASH       0x38040000      /* Address of relocated code */
 157 #define CONFIG_SYS_BL_START_RAM         0x03fd0000      /* Address of relocated code */
 158 #define CONFIG_SYS_MONITOR_BASE         TEXT_BASE
 159 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon       */
 160 #define CONFIG_SYS_FLASH_BASE           0x38000000      /* Boot Flash */
 161 #define CONFIG_SYS_FLASH_BASE_1         0x10000000      /* StrataFlash 1 */
 162 #define CONFIG_SYS_FLASH_BASE_2         0x11000000      /* StrataFlash 2 */
 163
 164 /* timeout values are in ticks */
 165 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 166 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 167
 168 /* allow to overwrite serial and ethaddr */
 169 #define CONFIG_ENV_OVERWRITE
 170
 171  /*-----------------------------------------------------------------------
 172   * FLASH configuration
 173   */
 174 #define CONFIG_FLASH_CFI_DRIVER                         /* Use the common driver */
 175 #define CONFIG_FLASH_CFI_LEGACY
 176 #define CONFIG_SYS_FLASH_CFI                            /* Flash is CFI conformant */
 177 #define CONFIG_SYS_MAX_FLASH_BANKS      3       /* max number of memory banks */
 178 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE,   \
 179                                          CONFIG_SYS_FLASH_BASE_1, \
 180                                          CONFIG_SYS_FLASH_BASE_2}
 181 #define CONFIG_SYS_FLASH_EMPTY_INFO
 182 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 183 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip */
 184 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_8BIT
 185 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
 186
 187  /*-----------------------------------------------------------------------
 188   * Environment configuration
 189   */
 190 #define CONFIG_ENV_IS_IN_FLASH          1
 191 #define CONFIG_ENV_OFFSET               0x20000 /*   Offset   of Environment Sector */
 192 #define CONFIG_ENV_SIZE                 0x08000 /* Total Size of Environment Sector */
 193 #define CONFIG_ENV_SECT_SIZE            0x20000 /* Total Size of Environment Sector */
 194 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE_1 + \
 195                                          CONFIG_ENV_OFFSET)
 196 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 197                                          CONFIG_ENV_SECT_SIZE)
 198 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 199
 200
 201  /*-----------------------------------------------------------------------
 202   * PCI configuration
 203   */
 204 #undef CONFIG_PCI                                /* include pci support */
 205 #undef CONFIG_PCI_PNP                            /* pci plug-and-play */
 206 #undef CONFIG_PCI_SCAN_SHOW
 207 #undef CONFIG_SYS_FIRST_PCI_IRQ
 208 #undef CONFIG_SYS_SECOND_PCI_IRQ
 209 #undef CONFIG_SYS_THIRD_PCI_IRQ
 210 #undef CONFIG_SYS_FORTH_PCI_IRQ
 211
 212 /*-----------------------------------------------------------------------
 213  * Hardware watchdog configuration
 214  */
 215 #define CONFIG_SYS_WATCHDOG_PIO_BIT             0x8000
 216 #define CONFIG_SYS_WATCHDIG_PIO_DATA            SC520_PIODATA15_0
 217 #define CONFIG_SYS_WATCHDIG_PIO_CLR             SC520_PIOCLR15_0
 218 #define CONFIG_SYS_WATCHDIG_PIO_SET             SC520_PIOSET15_0
 219
 220 /*-----------------------------------------------------------------------
 221  * FPGA configuration
 222  */
 223 #define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT         0x2000
 224 #define CONFIG_SYS_FPGA_INIT_PIO_BIT            0x4000
 225 #define CONFIG_SYS_FPGA_DONE_PIO_BIT            0x8000
 226 #define CONFIG_SYS_FPGA_PIO_DATA                SC520_PIODATA31_16
 227 #define CONFIG_SYS_FPGA_PIO_DIRECTION           SC520_PIODIR31_16
 228 #define CONFIG_SYS_FPGA_PIO_CLR                 SC520_PIOCLR31_16
 229 #define CONFIG_SYS_FPGA_PIO_SET                 SC520_PIOSET31_16
 230 #define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME   1       /* milliseconds */
 231 #define CONFIG_SYS_FPGA_MAX_INIT_TIME           10      /* milliseconds */
 232 #define CONFIG_SYS_FPGA_MAX_FINALISE_TIME       10      /* milliseconds */
 233 #define CONFIG_SYS_FPGA_SSI_DATA_RATE           8333    /* kHz (33.3333MHz xtal) */
 234
 235 #ifndef __ASSEMBLER__
 236 extern unsigned long ip;
 237
 238 #define PRINTIP                         asm ("call next_line\n" \
 239                                             "next_line:\n" \
 240                                             "pop %%eax\n" \
 241                                             "movl %%eax, %0\n" \
 242                                             :"=r"(ip) \
 243                                             : /* No Input Registers */ \
 244                                             :"%eax"); \
 245                                             printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__);
 246
 247 #endif
 248 #endif  /* __CONFIG_H */