1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
6 #ifndef _CONFIG_SYNOLOGY_DS414_H
7 #define _CONFIG_SYNOLOGY_DS414_H
10 * High Level Configuration Options (easy to change)
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
18 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
21 #define CONFIG_SYS_I2C
22 #define CONFIG_SYS_I2C_MVTWSI
23 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
24 #define CONFIG_SYS_I2C_SLAVE 0x0
25 #define CONFIG_SYS_I2C_SPEED 100000
28 #ifndef CONFIG_SPL_BUILD
29 #define CONFIG_PCI_SCAN_SHOW
32 /* USB/EHCI/XHCI configuration */
33 #define CONFIG_EHCI_IS_TDI
36 * mv-common.h should be defined after CMD configs since it used them
37 * to enable certain macros
39 #include "mv-common.h"
42 * Memory layout while starting into the bin_hdr via the
45 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
46 * 0x4000.4030 bin_hdr start address
47 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
48 * 0x4007.fffc BootROM stack top
50 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
51 * L2 cache thus cannot be used.
56 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
58 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
59 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
61 #ifdef CONFIG_SPL_BUILD
62 #define CONFIG_SYS_MALLOC_SIMPLE
65 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
66 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
68 #if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
69 /* SPL related SPI defines */
70 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
73 /* DS414 bus width is 32bits */
74 #define CONFIG_DDR_32BIT
76 /* Default Environment */
77 #define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
78 #define CONFIG_LOADADDR 0x80000
80 /* increase autoneg timeout, my NIC sucks */
81 #define PHY_ANEG_TIMEOUT 16000
83 #endif /* _CONFIG_SYNOLOGY_DS414_H */