1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Texas Instruments Incorporated.
5 * Lokesh Vutla <lokeshvutla@ti.com>
7 * Configuration settings for the TI DRA7XX board.
8 * See ti_omap5_common.h for omap5 common settings.
11 #ifndef __CONFIG_DRA7XX_EVM_H
12 #define __CONFIG_DRA7XX_EVM_H
14 #include <environment/ti/dfu.h>
16 #define CONFIG_IODELAY_RECALIBRATION
18 #define CONFIG_VERY_BIG_RAM
19 #define CONFIG_MAX_MEM_MAPPED 0x80000000
21 #ifndef CONFIG_QSPI_BOOT
22 /* MMC ENV related defines */
23 #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
24 #define CONFIG_ENV_SIZE (128 << 10)
25 #define CONFIG_ENV_OFFSET 0x260000
26 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
27 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
30 #if (CONFIG_CONS_INDEX == 1)
31 #define CONSOLEDEV "ttyO0"
32 #elif (CONFIG_CONS_INDEX == 3)
33 #define CONSOLEDEV "ttyO2"
35 #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
36 #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
37 #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
39 #define CONFIG_ENV_EEPROM_IS_ON_I2C
40 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
41 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
43 #define CONFIG_SYS_OMAP_ABE_SYSCK
45 #ifndef CONFIG_SPL_BUILD
47 "dfu_bufsiz=0x10000\0" \
54 #ifdef CONFIG_SPL_BUILD
55 #undef CONFIG_CMD_BOOTD
57 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
59 "dfu_bufsiz=0x10000\0" \
64 #include <configs/ti_omap5_common.h>
66 /* Enhance our eMMC support / experience. */
67 #define CONFIG_HSMMC2_8BIT
70 #define CONFIG_BOOTP_DNS2
71 #define CONFIG_BOOTP_SEND_HOSTNAME
72 #define CONFIG_NET_RETRY_COUNT 10
76 * Default to using SPI for environment, etc.
77 * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
78 * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
79 * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
80 * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
81 * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
82 * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
83 * 0x9E0000 - 0x2000000 : USERLAND
85 #define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
86 #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
87 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
88 #if defined(CONFIG_QSPI_BOOT)
89 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
90 #define CONFIG_ENV_SIZE (64 << 10)
91 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
92 #define CONFIG_ENV_OFFSET 0x1C0000
93 #define CONFIG_ENV_OFFSET_REDUND 0x1D0000
97 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
100 #define CONFIG_USB_XHCI_OMAP
102 #define CONFIG_OMAP_USB2PHY2_HOST
105 #define CONFIG_SCSI_AHCI_PLAT
109 /* NAND: device related configs */
110 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
111 #define CONFIG_SYS_NAND_OOBSIZE 64
112 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
113 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
114 CONFIG_SYS_NAND_PAGE_SIZE)
115 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
116 /* NAND: driver related configs */
117 #define CONFIG_SYS_NAND_ONFI_DETECTION
118 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
119 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
120 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
121 10, 11, 12, 13, 14, 15, 16, 17, \
122 18, 19, 20, 21, 22, 23, 24, 25, \
123 26, 27, 28, 29, 30, 31, 32, 33, \
124 34, 35, 36, 37, 38, 39, 40, 41, \
125 42, 43, 44, 45, 46, 47, 48, 49, \
126 50, 51, 52, 53, 54, 55, 56, 57, }
127 #define CONFIG_SYS_NAND_ECCSIZE 512
128 #define CONFIG_SYS_NAND_ECCBYTES 14
129 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00140000
130 /* NAND: SPL related configs */
131 /* NAND: SPL falcon mode configs */
132 #ifdef CONFIG_SPL_OS_BOOT
133 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
135 #endif /* !CONFIG_NAND */
137 /* Parallel NOR Support */
138 #if defined(CONFIG_NOR)
139 /* NOR: device related configs */
140 #define CONFIG_SYS_MAX_FLASH_SECT 512
141 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
142 #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
143 /* #define CONFIG_INIT_IGNORE_ERROR */
144 #define CONFIG_SYS_MAX_FLASH_BANKS 1
145 #define CONFIG_SYS_FLASH_BASE (0x08000000)
146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
147 /* Reduce SPL size by removing unlikey targets */
148 #ifdef CONFIG_NOR_BOOT
149 #define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */
150 #define CONFIG_ENV_OFFSET 0x001c0000
151 #define CONFIG_ENV_OFFSET_REDUND 0x001e0000
153 #endif /* NOR support */
155 #endif /* __CONFIG_DRA7XX_EVM_H */