3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #define CONFIG_405EP 1 /* this is a PPC405 CPU */
28 #define CONFIG_4xx 1 /* member of PPC4xx family */
29 #define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
31 #define CONFIG_SYS_TEXT_BASE 0xFFFC0000
34 * Include common defines/options for all AMCC eval boards
36 #define CONFIG_HOSTNAME dlvsion-10g
37 #define CONFIG_IDENT_STRING " dlvision-10g 0.01"
38 #include "amcc-common.h"
40 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
41 #define CONFIG_LAST_STAGE_INIT
43 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
48 #define PLLMR0_DEFAULT PLLMR0_266_133_66
49 #define PLLMR1_DEFAULT PLLMR1_266_133_66
51 /* new uImage format support */
53 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
55 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
58 * Default environment variables
60 #define CONFIG_EXTRA_ENV_SETTINGS \
62 CONFIG_AMCC_DEF_ENV_POWERPC \
63 CONFIG_AMCC_DEF_ENV_NOR_UPD \
64 "kernel_addr=fc000000\0" \
65 "fdt_addr=fc1e0000\0" \
66 "ramdisk_addr=fc200000\0" \
69 #define CONFIG_PHY_ADDR 4 /* PHY address */
70 #define CONFIG_HAS_ETH0
71 #define CONFIG_HAS_ETH1
72 #define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
73 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
76 * Commands additional to the ones defined in amcc-common.h
78 #define CONFIG_CMD_CACHE
79 #undef CONFIG_CMD_EEPROM
82 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
84 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
86 /* SDRAM timings used in datasheet */
87 #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
88 #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
89 #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
90 #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
91 #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
94 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
95 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
96 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
97 * The Linux BASE_BAUD define should match this configuration.
98 * baseBaud = cpuClock/(uartDivisor*16)
99 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
100 * set Linux BASE_BAUD to 403200.
102 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
103 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
104 #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
105 #define CONFIG_SYS_BASE_BAUD 691200
110 #define CONFIG_SYS_I2C_SPEED 100000
112 /* Temp sensor/hwmon/dtt */
113 #define CONFIG_DTT_LM63 1 /* National LM63 */
114 #define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
115 #define CONFIG_DTT_PWM_LOOKUPTABLE \
116 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
117 #define CONFIG_DTT_TACH_LIMIT 0xa10
119 /* EBC peripherals */
121 #define CONFIG_SYS_FLASH_BASE 0xFC000000
122 #define CONFIG_SYS_FPGA0_BASE 0x7f100000
123 #define CONFIG_SYS_FPGA1_BASE 0x7f200000
124 #define CONFIG_SYS_LATCH_BASE 0x7f300000
126 #define CONFIG_SYS_FPGA_BASE(k) \
127 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
129 #define CONFIG_SYS_FPGA_DONE(k) \
130 (k ? 0x2000 : 0x1000)
132 #define CONFIG_SYS_FPGA_COUNT 2
134 #define CONFIG_SYS_LATCH0_RESET 0xffff
135 #define CONFIG_SYS_LATCH0_BOOT 0xffff
136 #define CONFIG_SYS_LATCH1_RESET 0xffcf
137 #define CONFIG_SYS_LATCH1_BOOT 0xffff
142 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
143 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
145 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
147 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
148 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
150 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
151 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
153 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
154 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
156 #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
157 #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
159 #ifdef CONFIG_ENV_IS_IN_FLASH
160 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
161 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
162 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
164 /* Address and size of Redundant Environment Sector */
165 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
166 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
170 * PPC405 GPIO Configuration
172 #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
175 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
176 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
177 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
178 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
179 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
180 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
181 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
182 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
183 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
184 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
185 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
186 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
187 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
188 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
189 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
190 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
191 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
192 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
193 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
194 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
195 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
196 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
197 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
198 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
199 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
200 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
201 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
202 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
203 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
204 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
205 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
206 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
211 * Definitions for initial stack pointer and data area (in data cache)
213 /* use on chip memory (OCM) for temperary stack until sdram is tested */
214 #define CONFIG_SYS_TEMP_STACK_OCM 1
216 /* On Chip Memory location */
217 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
218 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
219 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
220 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
222 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
223 #define CONFIG_SYS_GBL_DATA_OFFSET \
224 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
225 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
228 * External Bus Controller (EBC) Setup
231 /* Memory Bank 0 (NOR-flash) */
232 #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
233 EBC_BXAP_FWT_ENCODE(8) | \
234 EBC_BXAP_BWT_ENCODE(7) | \
235 EBC_BXAP_BCE_DISABLE | \
236 EBC_BXAP_BCT_2TRANS | \
237 EBC_BXAP_CSN_ENCODE(0) | \
238 EBC_BXAP_OEN_ENCODE(2) | \
239 EBC_BXAP_WBN_ENCODE(2) | \
240 EBC_BXAP_WBF_ENCODE(2) | \
241 EBC_BXAP_TH_ENCODE(4) | \
242 EBC_BXAP_RE_DISABLED | \
243 EBC_BXAP_SOR_NONDELAYED | \
244 EBC_BXAP_BEM_WRITEONLY | \
245 EBC_BXAP_PEN_DISABLED)
246 #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
251 /* Memory Bank 1 (FPGA0) */
252 #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
253 EBC_BXAP_TWT_ENCODE(5) | \
254 EBC_BXAP_BCE_DISABLE | \
255 EBC_BXAP_BCT_2TRANS | \
256 EBC_BXAP_CSN_ENCODE(0) | \
257 EBC_BXAP_OEN_ENCODE(2) | \
258 EBC_BXAP_WBN_ENCODE(1) | \
259 EBC_BXAP_WBF_ENCODE(1) | \
260 EBC_BXAP_TH_ENCODE(0) | \
261 EBC_BXAP_RE_DISABLED | \
262 EBC_BXAP_SOR_NONDELAYED | \
263 EBC_BXAP_BEM_WRITEONLY | \
264 EBC_BXAP_PEN_DISABLED)
265 #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
270 /* Memory Bank 2 (FPGA1) */
271 #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
272 EBC_BXAP_TWT_ENCODE(6) | \
273 EBC_BXAP_BCE_DISABLE | \
274 EBC_BXAP_BCT_2TRANS | \
275 EBC_BXAP_CSN_ENCODE(0) | \
276 EBC_BXAP_OEN_ENCODE(2) | \
277 EBC_BXAP_WBN_ENCODE(1) | \
278 EBC_BXAP_WBF_ENCODE(1) | \
279 EBC_BXAP_TH_ENCODE(0) | \
280 EBC_BXAP_RE_DISABLED | \
281 EBC_BXAP_SOR_NONDELAYED | \
282 EBC_BXAP_BEM_WRITEONLY | \
283 EBC_BXAP_PEN_DISABLED)
284 #define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
289 /* Memory Bank 3 (Latches) */
290 #define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
291 EBC_BXAP_FWT_ENCODE(8) | \
292 EBC_BXAP_BWT_ENCODE(4) | \
293 EBC_BXAP_BCE_DISABLE | \
294 EBC_BXAP_BCT_2TRANS | \
295 EBC_BXAP_CSN_ENCODE(0) | \
296 EBC_BXAP_OEN_ENCODE(1) | \
297 EBC_BXAP_WBN_ENCODE(1) | \
298 EBC_BXAP_WBF_ENCODE(1) | \
299 EBC_BXAP_TH_ENCODE(2) | \
300 EBC_BXAP_RE_DISABLED | \
301 EBC_BXAP_SOR_NONDELAYED | \
302 EBC_BXAP_BEM_WRITEONLY | \
303 EBC_BXAP_PEN_DISABLED)
304 #define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
312 #define CONFIG_SYS_ICS8N3QV01
313 #define CONFIG_SYS_SIL1178
314 #define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
316 #endif /* __CONFIG_H */