include/configs/digsy_mtc.h

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2005-2007
   6  * Modified for InterControl digsyMTC MPC5200 board by
   7  * Frank Bodammer, GCD Hard- & Software GmbH,
   8  *                 frank.bodammer@gcd-solutions.de
   9  *
  10  * (C) Copyright 2009 Semihalf
  11  * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU */
  24 #define CONFIG_DIGSY_MTC        1       /* ... on InterControl digsyMTC board */
  25
  26 /*
  27  * Valid values for CONFIG_SYS_TEXT_BASE are:
  28  * 0xFFF00000   boot high (standard configuration)
  29  * 0xFE000000   boot low
  30  * 0x00100000   boot from RAM (for testing only)
  31  */
  32 #ifndef CONFIG_SYS_TEXT_BASE
  33 #define CONFIG_SYS_TEXT_BASE    0xFFF00000      /* Standard: boot high */
  34 #endif
  35
  36 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000
  37
  38 #define CONFIG_SYS_CACHELINE_SIZE       32
  39
  40 /*
  41  * Serial console configuration
  42  */
  43 #define CONFIG_PSC_CONSOLE      4       /* console is on PSC4  */
  44 #define CONFIG_BAUDRATE         115200  /* ... at 115200  bps  */
  45 #define CONFIG_SYS_BAUDRATE_TABLE       \
  46         { 9600, 19200, 38400, 57600, 115200, 230400 }
  47
  48 /*
  49  * PCI Mapping:
  50  * 0x40000000 - 0x4fffffff - PCI Memory
  51  * 0x50000000 - 0x50ffffff - PCI IO Space
  52  */
  53 #define CONFIG_PCI_PNP          1
  54 #define CONFIG_PCI_SCAN_SHOW    1
  55 #define CONFIG_PCI_BOOTDELAY    250
  56
  57 #define CONFIG_PCI_MEM_BUS      0x40000000
  58 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  59 #define CONFIG_PCI_MEM_SIZE     0x10000000
  60
  61 #define CONFIG_PCI_IO_BUS       0x50000000
  62 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  63 #define CONFIG_PCI_IO_SIZE      0x01000000
  64
  65 /*
  66  *  Partitions
  67  */
  68 #define CONFIG_DOS_PARTITION
  69 #define CONFIG_BZIP2
  70
  71 /*
  72  * Video
  73  */
  74
  75 #ifdef CONFIG_VIDEO
  76 #define CONFIG_VIDEO_MB862xx
  77 #define CONFIG_VIDEO_MB862xx_ACCEL
  78 #define CONFIG_VIDEO_CORALP
  79 #define CONFIG_VIDEO_LOGO
  80 #define CONFIG_VIDEO_BMP_LOGO
  81 #define CONFIG_SPLASH_SCREEN
  82 #define CONFIG_VIDEO_BMP_GZIP
  83 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)       /* decompressed img */
  84
  85 /* Coral-PA clock frequency, geo and other both 133MHz */
  86 #define CONFIG_SYS_MB862xx_CCF  0x00050000
  87 /* Video SDRAM parameters */
  88 #define CONFIG_SYS_MB862xx_MMR  0x11d7fa72
  89 #endif
  90
  91 /*
  92  * Command line configuration.
  93  */
  94 #ifdef CONFIG_VIDEO
  95 #define CONFIG_CMD_BMP
  96 #endif
  97 #define CONFIG_CMD_DATE
  98 #define CONFIG_CMD_DIAG
  99 #define CONFIG_CMD_EEPROM
 100 #define CONFIG_CMD_IDE
 101 #define CONFIG_CMD_IRQ
 102 #define CONFIG_CMD_PCI
 103 #define CONFIG_CMD_REGINFO
 104 #define CONFIG_CMD_SAVES
 105
 106 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
 107 #define CONFIG_SYS_LOWBOOT      1
 108 #endif
 109
 110 /*
 111  * Autobooting
 112  */
 113
 114 #undef  CONFIG_BOOTARGS
 115
 116 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 117         "fw_image=digsyMPC.img\0"                                       \
 118         "mtcb_start=mtc led diag orange; run mtcb_1\0"                  \
 119         "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; "           \
 120                 "do mtc led $x; done\0"                                 \
 121         "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; "       \
 122                 "else run mtcb_fw; fi\0"                                \
 123         "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; "           \
 124                 "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0"   \
 125         "mtcb_update=mtc led user1 orange;"                             \
 126                 "while mtc key; do ; done; run mtcb_2;\0"               \
 127         "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0"     \
 128         "mtcb_usb1=if fatload usb 0 400000 script.img; "                \
 129                 "then run mtcb_doscript; else run mtcb_usb2; fi\0"      \
 130         "mtcb_usb2=if fatload usb 0 400000 $fw_image; "                 \
 131                 "then run mtcb_dousb; else run mtcb_ide; fi\0"          \
 132         "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; "      \
 133                 "run mtcb_wait_flickr mtcb_ds_1;\0"                     \
 134         "mtcb_ds_1=if imi 400000; then mtc led usbbusy; "               \
 135                 "source 400000; else run mtcb_error; fi\0"              \
 136         "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0"     \
 137         "mtcb_du_1=if imi 400000; then run mtcb_du_2; "                 \
 138                 "else run mtcb_error; fi\0"                             \
 139         "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; "         \
 140                 "run mtcb_checkfw\0"                                    \
 141         "mtcb_checkfw=if imi ff000000; then run mtcb_success; "         \
 142                 "else run mtcb_error; fi\0"                             \
 143         "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
 144         "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0"            \
 145         "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
 146         "mtcb_uledflckr=mtc led user1 orange 11\0"                      \
 147         "mtcb_error=mtc led user1 red\0"                                \
 148         "mtcb_clear=erase ff000000 ff0fffff\0"                          \
 149         "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0"                  \
 150         "mtcb_success=mtc led user1 green\0"                            \
 151         "mtcb_ide=if fatload ide 0 400000 $fw_image;"                   \
 152                 "then run mtcb_doide; else run mtcb_error; fi\0"        \
 153         "mtcb_doide=mtc led user2 green 1;"                             \
 154                 "run mtcb_wait_flickr mtcb_di_1;\0"                     \
 155         "mtcb_di_1=if imi 400000; then run mtcb_di_2;"                  \
 156                 "else run mtcb_error; fi\0"                             \
 157         "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0"        \
 158         "ramdisk_num_sector=16\0"                                       \
 159         "flash_base=ff000000\0"                                         \
 160         "flashdisk_size=e00000\0"                                       \
 161         "env_sector=fff60000\0"                                         \
 162         "flashdisk_start=ff100000\0"                                    \
 163         "load_cmd=tftp 400000 digsyMPC.img\0"                           \
 164         "clear_cmd=erase ff000000 ff0fffff\0"                           \
 165         "flash_cmd=cp.b 400000 ff000000 ${filesize}\0"                  \
 166         "update_cmd=run load_cmd; "                                     \
 167         "iminfo 400000; "                                               \
 168         "run clear_cmd flash_cmd; "                                     \
 169         "iminfo ff000000\0"                                             \
 170         "spi_driver=yes\0"                                              \
 171         "spi_watchdog=no\0"                                             \
 172         "ftps_start=yes\0"                                              \
 173         "ftps_user1=admin\0"                                            \
 174         "ftps_pass1=admin\0"                                            \
 175         "ftps_base1=/\0"                                                \
 176         "ftps_home1=/\0"                                                \
 177         "plc_sio_srv=no\0"                                              \
 178         "plc_sio_baud=57600\0"                                          \
 179         "plc_sio_parity=no\0"                                           \
 180         "plc_sio_stop=1\0"                                              \
 181         "plc_sio_com=2\0"                                               \
 182         "plc_eth_srv=yes\0"                                             \
 183         "plc_eth_port=1200\0"                                           \
 184         "plc_root=/ide/\0"                                              \
 185         "diag_level=0\0"                                                \
 186         "webvisu=no\0"                                                  \
 187         "plc_can1_routing=no\0"                                         \
 188         "plc_can1_baudrate=250\0"                                       \
 189         "plc_can2_routing=no\0"                                         \
 190         "plc_can2_baudrate=250\0"                                       \
 191         "plc_can3_routing=no\0"                                         \
 192         "plc_can3_baudrate=250\0"                                       \
 193         "plc_can4_routing=no\0"                                         \
 194         "plc_can4_baudrate=250\0"                                       \
 195         "netdev=eth0\0"                                                 \
 196         "console=ttyPSC0\0"                                             \
 197         "kernel_addr_r=400000\0"                                        \
 198         "fdt_addr_r=600000\0"                                           \
 199         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 200         "nfsroot=${serverip}:${rootpath}\0"                             \
 201         "addip=setenv bootargs ${bootargs} "                            \
 202         "ip=${ipaddr}:${serverip}:${gatewayip}:"                        \
 203         "${netmask}:${hostname}:${netdev}:off panic=1\0"                \
 204         "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
 205         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 206         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 207                 "tftp ${fdt_addr_r} ${fdt_file};"                       \
 208                 "run nfsargs addip addcons;"                            \
 209                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 210         "load=tftp 200000 ${u-boot}\0"                                  \
 211         "update=protect off FFF00000 +${filesize};"                     \
 212                 "erase FFF00000 +${filesize};"                          \
 213                 "cp.b 200000 FFF00000 ${filesize};"                     \
 214                 "protect on FFF00000 +${filesize}\0"                    \
 215         ""
 216
 217 #define CONFIG_BOOTCOMMAND      "run mtcb_start"
 218
 219 /*
 220  * SPI configuration
 221  */
 222 #define CONFIG_HARD_SPI         1
 223 #define CONFIG_MPC52XX_SPI      1
 224
 225 /*
 226  * I2C configuration
 227  */
 228 #define CONFIG_HARD_I2C         1
 229 #define CONFIG_SYS_I2C_MODULE   1
 230 #define CONFIG_SYS_I2C_SPEED    100000
 231 #define CONFIG_SYS_I2C_SLAVE    0x7F
 232
 233 /*
 234  * EEPROM configuration
 235  */
 236 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 237 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 238 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 239 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 240
 241 /*
 242  * RTC configuration
 243  */
 244 #if defined(CONFIG_DIGSY_REV5)
 245 #define CONFIG_SYS_I2C_RTC_ADDR 0x56
 246 #define CONFIG_RTC_RV3029
 247 /* Enable 5k Ohm trickle charge resistor */
 248 #define CONFIG_SYS_RV3029_TCR   0x20
 249 #else
 250 #define CONFIG_RTC_DS1337
 251 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 252 #define CONFIG_SYS_DS1339_TCR_VAL       0xAB    /* diode + 4k resistor */
 253 #endif
 254
 255 /*
 256  * Flash configuration
 257  */
 258 #define CONFIG_SYS_FLASH_CFI            1
 259 #define CONFIG_FLASH_CFI_DRIVER 1
 260
 261 #if defined(CONFIG_DIGSY_REV5)
 262 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 263 #define CONFIG_SYS_FLASH_BASE_CS1       0xFC000000
 264 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 265 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, \
 266                                         CONFIG_SYS_FLASH_BASE_CS1}
 267 #define CONFIG_SYS_UPDATE_FLASH_SIZE
 268 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 269 #else
 270 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 271 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 272 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 273 #endif
 274
 275 #define CONFIG_SYS_MAX_FLASH_SECT       256
 276 #define CONFIG_FLASH_16BIT
 277 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
 278 #define CONFIG_SYS_FLASH_SIZE   0x01000000
 279 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000
 280 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
 281
 282 #define OF_CPU                  "PowerPC,5200@0"
 283 #define OF_SOC                  "soc5200@f0000000"
 284 #define OF_TBCLK                (bd->bi_busfreq / 4)
 285
 286 #define CONFIG_BOARD_EARLY_INIT_R
 287 #define CONFIG_MISC_INIT_R
 288
 289 /*
 290  * Environment settings
 291  */
 292 #define CONFIG_ENV_IS_IN_FLASH  1
 293 #if defined(CONFIG_LOWBOOT)
 294 #define CONFIG_ENV_ADDR         0xFF060000
 295 #else   /* CONFIG_LOWBOOT */
 296 #define CONFIG_ENV_ADDR         0xFFF60000
 297 #endif  /* CONFIG_LOWBOOT */
 298 #define CONFIG_ENV_SIZE         0x10000
 299 #define CONFIG_ENV_SECT_SIZE    0x20000
 300 #define CONFIG_ENV_OVERWRITE    1
 301
 302 /*
 303  * Memory map
 304  */
 305 #define CONFIG_SYS_MBAR         0xF0000000
 306 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 307 #if !defined(CONFIG_SYS_LOWBOOT)
 308 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 309 #else
 310 #define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
 311 #endif
 312
 313 /*
 314  *  Use SRAM until RAM will be available
 315  */
 316 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 317 #define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE
 318
 319 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 320         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 321 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 322
 323 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 324 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 325 #define CONFIG_SYS_RAMBOOT              1
 326 #endif
 327
 328 #define CONFIG_SYS_MONITOR_LEN  (256 << 10)
 329 #define CONFIG_SYS_MALLOC_LEN   (4096 << 10)
 330 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)
 331
 332 /*
 333  * Ethernet configuration
 334  */
 335 #define CONFIG_MPC5xxx_FEC      1
 336 #define CONFIG_MPC5xxx_FEC_MII100
 337 #if defined(CONFIG_DIGSY_REV5)
 338 #define CONFIG_PHY_ADDR         0x01
 339 #else
 340 #define CONFIG_PHY_ADDR         0x00
 341 #endif
 342 #define CONFIG_PHY_RESET_DELAY  1000
 343
 344 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 345
 346 /*
 347  * GPIO configuration
 348  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
 349  *  Bit 0   (mask 0x80000000) : 0x1
 350  * SPI on Tmr2/3/4/5 pins
 351  *  Bit 2:3 (mask 0x30000000) : 0x2
 352  * ATA cs0/1 on csb_4/5
 353  *  Bit 6:7 (mask 0x03000000) : 0x2
 354  * Ethernet 100Mbit with MD
 355  *  Bits 12:15 (mask 0x000f0000): 0x5
 356  * USB - Two UARTs
 357  *  Bits 18:19 (mask 0x00003000) : 0x2
 358  * PSC3 - USB2 on PSC3
 359  *  Bits 20:23 (mask 0x00000f00) : 0x1
 360  * PSC2 - CAN1&2 on PSC2 pins
 361  *  Bits 25:27 (mask 0x00000070) : 0x1
 362  * PSC1 - AC97 functionality
 363  *  Bits 29:31 (mask 0x00000007) : 0x2
 364  */
 365 #define CONFIG_SYS_GPS_PORT_CONFIG      0xA2552112
 366
 367 /*
 368  * Miscellaneous configurable options
 369  */
 370 #define CONFIG_SYS_LONGHELP
 371 #define CONFIG_AUTO_COMPLETE    1
 372 #define CONFIG_CMDLINE_EDITING  1
 373
 374 #define CONFIG_MX_CYCLIC        1
 375
 376 #define CONFIG_SYS_CBSIZE               1024
 377 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 378 #define CONFIG_SYS_MAXARGS              32
 379 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 380
 381 #define CONFIG_SYS_ALT_MEMTEST
 382 #define CONFIG_SYS_MEMTEST_SCRATCH      0x00001000
 383 #define CONFIG_SYS_MEMTEST_START        0x00010000
 384 #define CONFIG_SYS_MEMTEST_END          0x019fffff
 385
 386 #define CONFIG_SYS_LOAD_ADDR            0x00100000
 387
 388 /*
 389  * Various low-level settings
 390  */
 391 #define CONFIG_SYS_SDRAM_CS1            1
 392 #define CONFIG_SYS_XLB_PIPELINING       1
 393
 394 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 395 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 396
 397 #if defined(CONFIG_SYS_LOWBOOT)
 398 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 399 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 400 #define CONFIG_SYS_BOOTCS_CFG           0x0002DD00
 401 #endif
 402
 403 #define CONFIG_SYS_CS4_START            0x60000000
 404 #define CONFIG_SYS_CS4_SIZE             0x1000
 405 #define CONFIG_SYS_CS4_CFG              0x0008FC00
 406
 407 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 408 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 409 #define CONFIG_SYS_CS0_CFG              0x0002DD00
 410
 411 #if defined(CONFIG_DIGSY_REV5)
 412 #define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH_BASE_CS1
 413 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_FLASH_SIZE
 414 #define CONFIG_SYS_CS1_CFG              0x0002DD00
 415 #endif
 416
 417 #define CONFIG_SYS_CS_BURST             0x00000000
 418 #define CONFIG_SYS_CS_DEADCYCLE 0x11111111
 419
 420 #if !defined(CONFIG_SYS_LOWBOOT)
 421 #define CONFIG_SYS_RESET_ADDRESS        0xfff00100
 422 #else
 423 #define CONFIG_SYS_RESET_ADDRESS        0xff000100
 424 #endif
 425
 426 /*
 427  * USB
 428  */
 429 #define CONFIG_USB_OHCI_NEW
 430 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 431
 432 #define CONFIG_USB_CLOCK        0x00013333
 433 #define CONFIG_USB_CONFIG       0x00002000
 434
 435 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 436 #define CONFIG_SYS_USB_OHCI_REGS_BASE   MPC5XXX_USB
 437 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "mpc5200"
 438 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 439
 440 /*
 441  * IDE/ATA
 442  */
 443 #define CONFIG_IDE_RESET
 444 #define CONFIG_IDE_PREINIT
 445
 446 #define CONFIG_SYS_ATA_CS_ON_I2C2
 447 #define CONFIG_SYS_IDE_MAXBUS           1
 448 #define CONFIG_SYS_IDE_MAXDEVICE        1
 449
 450 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 451 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 452 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 453 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 454 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 455 #define CONFIG_SYS_ATA_STRIDE           4
 456
 457 #define CONFIG_ATAPI            1
 458 #define CONFIG_LBA48            1
 459
 460 #endif /* __CONFIG_H */