2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2005-2007
6 * Modified for InterControl digsyMTC MPC5200 board by
7 * Frank Bodammer, GCD Hard- & Software GmbH,
8 * frank.bodammer@gcd-solutions.de
10 * (C) Copyright 2009 Semihalf
11 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
13 * SPDX-License-Identifier: GPL-2.0+
20 * High Level Configuration Options
23 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
24 #define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
27 * Valid values for CONFIG_SYS_TEXT_BASE are:
28 * 0xFFF00000 boot high (standard configuration)
30 * 0x00100000 boot from RAM (for testing only)
32 #ifndef CONFIG_SYS_TEXT_BASE
33 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
36 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000
38 #define CONFIG_SYS_CACHELINE_SIZE 32
41 * Serial console configuration
43 #define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
44 #define CONFIG_SYS_BAUDRATE_TABLE \
45 { 9600, 19200, 38400, 57600, 115200, 230400 }
49 * 0x40000000 - 0x4fffffff - PCI Memory
50 * 0x50000000 - 0x50ffffff - PCI IO Space
52 #define CONFIG_PCI_SCAN_SHOW 1
53 #define CONFIG_PCI_BOOTDELAY 250
55 #define CONFIG_PCI_MEM_BUS 0x40000000
56 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
57 #define CONFIG_PCI_MEM_SIZE 0x10000000
59 #define CONFIG_PCI_IO_BUS 0x50000000
60 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
61 #define CONFIG_PCI_IO_SIZE 0x01000000
70 #define CONFIG_VIDEO_MB862xx
71 #define CONFIG_VIDEO_MB862xx_ACCEL
72 #define CONFIG_VIDEO_CORALP
73 #define CONFIG_VIDEO_LOGO
74 #define CONFIG_VIDEO_BMP_LOGO
75 #define CONFIG_SPLASH_SCREEN
76 #define CONFIG_VIDEO_BMP_GZIP
77 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
79 /* Coral-PA clock frequency, geo and other both 133MHz */
80 #define CONFIG_SYS_MB862xx_CCF 0x00050000
81 /* Video SDRAM parameters */
82 #define CONFIG_SYS_MB862xx_MMR 0x11d7fa72
86 * Command line configuration.
89 #define CONFIG_CMD_BMP
91 #define CONFIG_CMD_DATE
92 #define CONFIG_CMD_DIAG
93 #define CONFIG_CMD_EEPROM
94 #define CONFIG_CMD_IDE
95 #define CONFIG_CMD_IRQ
96 #define CONFIG_CMD_PCI
97 #define CONFIG_CMD_REGINFO
98 #define CONFIG_CMD_SAVES
100 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
101 #define CONFIG_SYS_LOWBOOT 1
108 #undef CONFIG_BOOTARGS
110 #define CONFIG_EXTRA_ENV_SETTINGS \
111 "fw_image=digsyMPC.img\0" \
112 "mtcb_start=mtc led diag orange; run mtcb_1\0" \
113 "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \
114 "do mtc led $x; done\0" \
115 "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \
116 "else run mtcb_fw; fi\0" \
117 "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \
118 "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \
119 "mtcb_update=mtc led user1 orange;" \
120 "while mtc key; do ; done; run mtcb_2;\0" \
121 "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \
122 "mtcb_usb1=if fatload usb 0 400000 script.img; " \
123 "then run mtcb_doscript; else run mtcb_usb2; fi\0" \
124 "mtcb_usb2=if fatload usb 0 400000 $fw_image; " \
125 "then run mtcb_dousb; else run mtcb_ide; fi\0" \
126 "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \
127 "run mtcb_wait_flickr mtcb_ds_1;\0" \
128 "mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \
129 "source 400000; else run mtcb_error; fi\0" \
130 "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \
131 "mtcb_du_1=if imi 400000; then run mtcb_du_2; " \
132 "else run mtcb_error; fi\0" \
133 "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \
134 "run mtcb_checkfw\0" \
135 "mtcb_checkfw=if imi ff000000; then run mtcb_success; " \
136 "else run mtcb_error; fi\0" \
137 "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
138 "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \
139 "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
140 "mtcb_uledflckr=mtc led user1 orange 11\0" \
141 "mtcb_error=mtc led user1 red\0" \
142 "mtcb_clear=erase ff000000 ff0fffff\0" \
143 "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \
144 "mtcb_success=mtc led user1 green\0" \
145 "mtcb_ide=if fatload ide 0 400000 $fw_image;" \
146 "then run mtcb_doide; else run mtcb_error; fi\0" \
147 "mtcb_doide=mtc led user2 green 1;" \
148 "run mtcb_wait_flickr mtcb_di_1;\0" \
149 "mtcb_di_1=if imi 400000; then run mtcb_di_2;" \
150 "else run mtcb_error; fi\0" \
151 "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \
152 "ramdisk_num_sector=16\0" \
153 "flash_base=ff000000\0" \
154 "flashdisk_size=e00000\0" \
155 "env_sector=fff60000\0" \
156 "flashdisk_start=ff100000\0" \
157 "load_cmd=tftp 400000 digsyMPC.img\0" \
158 "clear_cmd=erase ff000000 ff0fffff\0" \
159 "flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \
160 "update_cmd=run load_cmd; " \
162 "run clear_cmd flash_cmd; " \
163 "iminfo ff000000\0" \
165 "spi_watchdog=no\0" \
167 "ftps_user1=admin\0" \
168 "ftps_pass1=admin\0" \
172 "plc_sio_baud=57600\0" \
173 "plc_sio_parity=no\0" \
176 "plc_eth_srv=yes\0" \
177 "plc_eth_port=1200\0" \
181 "plc_can1_routing=no\0" \
182 "plc_can1_baudrate=250\0" \
183 "plc_can2_routing=no\0" \
184 "plc_can2_baudrate=250\0" \
185 "plc_can3_routing=no\0" \
186 "plc_can3_baudrate=250\0" \
187 "plc_can4_routing=no\0" \
188 "plc_can4_baudrate=250\0" \
190 "console=ttyPSC0\0" \
191 "kernel_addr_r=400000\0" \
192 "fdt_addr_r=600000\0" \
193 "nfsargs=setenv bootargs root=/dev/nfs rw " \
194 "nfsroot=${serverip}:${rootpath}\0" \
195 "addip=setenv bootargs ${bootargs} " \
196 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
197 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
198 "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
199 "rootpath=/opt/eldk/ppc_6xx\0" \
200 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
201 "tftp ${fdt_addr_r} ${fdt_file};" \
202 "run nfsargs addip addcons;" \
203 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
204 "load=tftp 200000 ${u-boot}\0" \
205 "update=protect off FFF00000 +${filesize};" \
206 "erase FFF00000 +${filesize};" \
207 "cp.b 200000 FFF00000 ${filesize};" \
208 "protect on FFF00000 +${filesize}\0" \
211 #define CONFIG_BOOTCOMMAND "run mtcb_start"
216 #define CONFIG_HARD_I2C 1
217 #define CONFIG_SYS_I2C_MODULE 1
218 #define CONFIG_SYS_I2C_SPEED 100000
219 #define CONFIG_SYS_I2C_SLAVE 0x7F
222 * EEPROM configuration
224 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
225 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
226 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
227 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
232 #if defined(CONFIG_DIGSY_REV5)
233 #define CONFIG_SYS_I2C_RTC_ADDR 0x56
234 #define CONFIG_RTC_RV3029
235 /* Enable 5k Ohm trickle charge resistor */
236 #define CONFIG_SYS_RV3029_TCR 0x20
238 #define CONFIG_RTC_DS1337
239 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
240 #define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
244 * Flash configuration
246 #define CONFIG_SYS_FLASH_CFI 1
247 #define CONFIG_FLASH_CFI_DRIVER 1
249 #if defined(CONFIG_DIGSY_REV5)
250 #define CONFIG_SYS_FLASH_BASE 0xFE000000
251 #define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000
252 #define CONFIG_SYS_MAX_FLASH_BANKS 2
253 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
254 CONFIG_SYS_FLASH_BASE_CS1}
255 #define CONFIG_SYS_UPDATE_FLASH_SIZE
256 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
258 #define CONFIG_SYS_FLASH_BASE 0xFF000000
259 #define CONFIG_SYS_MAX_FLASH_BANKS 1
260 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
263 #define CONFIG_SYS_MAX_FLASH_SECT 256
264 #define CONFIG_FLASH_16BIT
265 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
266 #define CONFIG_SYS_FLASH_SIZE 0x01000000
267 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000
268 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
270 #define OF_CPU "PowerPC,5200@0"
271 #define OF_SOC "soc5200@f0000000"
272 #define OF_TBCLK (bd->bi_busfreq / 4)
274 #define CONFIG_BOARD_EARLY_INIT_R
275 #define CONFIG_MISC_INIT_R
278 * Environment settings
280 #define CONFIG_ENV_IS_IN_FLASH 1
281 #if defined(CONFIG_LOWBOOT)
282 #define CONFIG_ENV_ADDR 0xFF060000
283 #else /* CONFIG_LOWBOOT */
284 #define CONFIG_ENV_ADDR 0xFFF60000
285 #endif /* CONFIG_LOWBOOT */
286 #define CONFIG_ENV_SIZE 0x10000
287 #define CONFIG_ENV_SECT_SIZE 0x20000
288 #define CONFIG_ENV_OVERWRITE 1
293 #define CONFIG_SYS_MBAR 0xF0000000
294 #define CONFIG_SYS_SDRAM_BASE 0x00000000
295 #if !defined(CONFIG_SYS_LOWBOOT)
296 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
298 #define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
302 * Use SRAM until RAM will be available
304 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
305 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
307 #define CONFIG_SYS_GBL_DATA_OFFSET \
308 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
309 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
311 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
312 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
313 #define CONFIG_SYS_RAMBOOT 1
316 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
317 #define CONFIG_SYS_MALLOC_LEN (4096 << 10)
318 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
321 * Ethernet configuration
323 #define CONFIG_MPC5xxx_FEC 1
324 #define CONFIG_MPC5xxx_FEC_MII100
325 #if defined(CONFIG_DIGSY_REV5)
326 #define CONFIG_PHY_ADDR 0x01
328 #define CONFIG_PHY_ADDR 0x00
330 #define CONFIG_PHY_RESET_DELAY 1000
332 #define CONFIG_NETCONSOLE /* include NetConsole support */
336 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
337 * Bit 0 (mask 0x80000000) : 0x1
338 * SPI on Tmr2/3/4/5 pins
339 * Bit 2:3 (mask 0x30000000) : 0x2
340 * ATA cs0/1 on csb_4/5
341 * Bit 6:7 (mask 0x03000000) : 0x2
342 * Ethernet 100Mbit with MD
343 * Bits 12:15 (mask 0x000f0000): 0x5
345 * Bits 18:19 (mask 0x00003000) : 0x2
346 * PSC3 - USB2 on PSC3
347 * Bits 20:23 (mask 0x00000f00) : 0x1
348 * PSC2 - CAN1&2 on PSC2 pins
349 * Bits 25:27 (mask 0x00000070) : 0x1
350 * PSC1 - AC97 functionality
351 * Bits 29:31 (mask 0x00000007) : 0x2
353 #define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
356 * Miscellaneous configurable options
358 #define CONFIG_SYS_LONGHELP
359 #define CONFIG_AUTO_COMPLETE 1
360 #define CONFIG_CMDLINE_EDITING 1
362 #define CONFIG_MX_CYCLIC 1
364 #define CONFIG_SYS_CBSIZE 1024
365 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
366 #define CONFIG_SYS_MAXARGS 32
367 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
369 #define CONFIG_SYS_ALT_MEMTEST
370 #define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
371 #define CONFIG_SYS_MEMTEST_START 0x00010000
372 #define CONFIG_SYS_MEMTEST_END 0x019fffff
374 #define CONFIG_SYS_LOAD_ADDR 0x00100000
377 * Various low-level settings
379 #define CONFIG_SYS_SDRAM_CS1 1
380 #define CONFIG_SYS_XLB_PIPELINING 1
382 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
383 #define CONFIG_SYS_HID0_FINAL HID0_ICE
385 #if defined(CONFIG_SYS_LOWBOOT)
386 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
387 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
388 #define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
391 #define CONFIG_SYS_CS4_START 0x60000000
392 #define CONFIG_SYS_CS4_SIZE 0x1000
393 #define CONFIG_SYS_CS4_CFG 0x0008FC00
395 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
396 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
397 #define CONFIG_SYS_CS0_CFG 0x0002DD00
399 #if defined(CONFIG_DIGSY_REV5)
400 #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1
401 #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
402 #define CONFIG_SYS_CS1_CFG 0x0002DD00
405 #define CONFIG_SYS_CS_BURST 0x00000000
406 #define CONFIG_SYS_CS_DEADCYCLE 0x11111111
408 #if !defined(CONFIG_SYS_LOWBOOT)
409 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
411 #define CONFIG_SYS_RESET_ADDRESS 0xff000100
417 #define CONFIG_USB_OHCI_NEW
418 #define CONFIG_SYS_OHCI_BE_CONTROLLER
420 #define CONFIG_USB_CLOCK 0x00013333
421 #define CONFIG_USB_CONFIG 0x00002000
423 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
424 #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
425 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
426 #define CONFIG_SYS_USB_OHCI_CPU_INIT
431 #define CONFIG_IDE_RESET
432 #define CONFIG_IDE_PREINIT
434 #define CONFIG_SYS_ATA_CS_ON_I2C2
435 #define CONFIG_SYS_IDE_MAXBUS 1
436 #define CONFIG_SYS_IDE_MAXDEVICE 1
438 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
439 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
440 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
441 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
442 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
443 #define CONFIG_SYS_ATA_STRIDE 4
445 #define CONFIG_ATAPI 1
446 #define CONFIG_LBA48 1
448 #endif /* __CONFIG_H */