2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2005-2007
6 * Modified for InterControl digsyMTC MPC5200 board by
7 * Frank Bodammer, GCD Hard- & Software GmbH,
8 * frank.bodammer@gcd-solutions.de
10 * (C) Copyright 2009 Semihalf
11 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
13 * SPDX-License-Identifier: GPL-2.0+
20 * High Level Configuration Options
23 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
24 #define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
27 * Valid values for CONFIG_SYS_TEXT_BASE are:
28 * 0xFFF00000 boot high (standard configuration)
30 * 0x00100000 boot from RAM (for testing only)
32 #ifndef CONFIG_SYS_TEXT_BASE
33 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
36 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000
38 #define CONFIG_SYS_CACHELINE_SIZE 32
41 * Serial console configuration
43 #define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
44 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
45 #define CONFIG_SYS_BAUDRATE_TABLE \
46 { 9600, 19200, 38400, 57600, 115200, 230400 }
50 * 0x40000000 - 0x4fffffff - PCI Memory
51 * 0x50000000 - 0x50ffffff - PCI IO Space
54 #define CONFIG_PCI_PNP 1
55 #define CONFIG_PCI_SCAN_SHOW 1
56 #define CONFIG_PCI_BOOTDELAY 250
58 #define CONFIG_PCI_MEM_BUS 0x40000000
59 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
60 #define CONFIG_PCI_MEM_SIZE 0x10000000
62 #define CONFIG_PCI_IO_BUS 0x50000000
63 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
64 #define CONFIG_PCI_IO_SIZE 0x01000000
69 #define CONFIG_DOS_PARTITION
77 #define CONFIG_VIDEO_MB862xx
78 #define CONFIG_VIDEO_MB862xx_ACCEL
79 #define CONFIG_VIDEO_CORALP
80 #define CONFIG_VIDEO_LOGO
81 #define CONFIG_VIDEO_BMP_LOGO
82 #define CONFIG_VIDEO_SW_CURSOR
83 #define CONFIG_VGA_AS_SINGLE_DEVICE
84 #define CONFIG_SPLASH_SCREEN
85 #define CONFIG_VIDEO_BMP_GZIP
86 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
88 /* Coral-PA clock frequency, geo and other both 133MHz */
89 #define CONFIG_SYS_MB862xx_CCF 0x00050000
90 /* Video SDRAM parameters */
91 #define CONFIG_SYS_MB862xx_MMR 0x11d7fa72
95 * Command line configuration.
98 #define CONFIG_CMD_BMP
100 #define CONFIG_CMD_DATE
101 #define CONFIG_CMD_DIAG
102 #define CONFIG_CMD_EEPROM
103 #define CONFIG_CMD_IDE
104 #define CONFIG_CMD_IRQ
105 #define CONFIG_CMD_PCI
106 #define CONFIG_CMD_REGINFO
107 #define CONFIG_CMD_SAVES
109 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
110 #define CONFIG_SYS_LOWBOOT 1
117 #undef CONFIG_BOOTARGS
119 #define CONFIG_EXTRA_ENV_SETTINGS \
120 "fw_image=digsyMPC.img\0" \
121 "mtcb_start=mtc led diag orange; run mtcb_1\0" \
122 "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \
123 "do mtc led $x; done\0" \
124 "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \
125 "else run mtcb_fw; fi\0" \
126 "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \
127 "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \
128 "mtcb_update=mtc led user1 orange;" \
129 "while mtc key; do ; done; run mtcb_2;\0" \
130 "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \
131 "mtcb_usb1=if fatload usb 0 400000 script.img; " \
132 "then run mtcb_doscript; else run mtcb_usb2; fi\0" \
133 "mtcb_usb2=if fatload usb 0 400000 $fw_image; " \
134 "then run mtcb_dousb; else run mtcb_ide; fi\0" \
135 "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \
136 "run mtcb_wait_flickr mtcb_ds_1;\0" \
137 "mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \
138 "source 400000; else run mtcb_error; fi\0" \
139 "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \
140 "mtcb_du_1=if imi 400000; then run mtcb_du_2; " \
141 "else run mtcb_error; fi\0" \
142 "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \
143 "run mtcb_checkfw\0" \
144 "mtcb_checkfw=if imi ff000000; then run mtcb_success; " \
145 "else run mtcb_error; fi\0" \
146 "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
147 "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \
148 "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
149 "mtcb_uledflckr=mtc led user1 orange 11\0" \
150 "mtcb_error=mtc led user1 red\0" \
151 "mtcb_clear=erase ff000000 ff0fffff\0" \
152 "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \
153 "mtcb_success=mtc led user1 green\0" \
154 "mtcb_ide=if fatload ide 0 400000 $fw_image;" \
155 "then run mtcb_doide; else run mtcb_error; fi\0" \
156 "mtcb_doide=mtc led user2 green 1;" \
157 "run mtcb_wait_flickr mtcb_di_1;\0" \
158 "mtcb_di_1=if imi 400000; then run mtcb_di_2;" \
159 "else run mtcb_error; fi\0" \
160 "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \
161 "ramdisk_num_sector=16\0" \
162 "flash_base=ff000000\0" \
163 "flashdisk_size=e00000\0" \
164 "env_sector=fff60000\0" \
165 "flashdisk_start=ff100000\0" \
166 "load_cmd=tftp 400000 digsyMPC.img\0" \
167 "clear_cmd=erase ff000000 ff0fffff\0" \
168 "flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \
169 "update_cmd=run load_cmd; " \
171 "run clear_cmd flash_cmd; " \
172 "iminfo ff000000\0" \
174 "spi_watchdog=no\0" \
176 "ftps_user1=admin\0" \
177 "ftps_pass1=admin\0" \
181 "plc_sio_baud=57600\0" \
182 "plc_sio_parity=no\0" \
185 "plc_eth_srv=yes\0" \
186 "plc_eth_port=1200\0" \
190 "plc_can1_routing=no\0" \
191 "plc_can1_baudrate=250\0" \
192 "plc_can2_routing=no\0" \
193 "plc_can2_baudrate=250\0" \
194 "plc_can3_routing=no\0" \
195 "plc_can3_baudrate=250\0" \
196 "plc_can4_routing=no\0" \
197 "plc_can4_baudrate=250\0" \
199 "console=ttyPSC0\0" \
200 "kernel_addr_r=400000\0" \
201 "fdt_addr_r=600000\0" \
202 "nfsargs=setenv bootargs root=/dev/nfs rw " \
203 "nfsroot=${serverip}:${rootpath}\0" \
204 "addip=setenv bootargs ${bootargs} " \
205 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
206 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
207 "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
208 "rootpath=/opt/eldk/ppc_6xx\0" \
209 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
210 "tftp ${fdt_addr_r} ${fdt_file};" \
211 "run nfsargs addip addcons;" \
212 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
213 "load=tftp 200000 ${u-boot}\0" \
214 "update=protect off FFF00000 +${filesize};" \
215 "erase FFF00000 +${filesize};" \
216 "cp.b 200000 FFF00000 ${filesize};" \
217 "protect on FFF00000 +${filesize}\0" \
220 #define CONFIG_BOOTCOMMAND "run mtcb_start"
225 #define CONFIG_HARD_SPI 1
226 #define CONFIG_MPC52XX_SPI 1
231 #define CONFIG_HARD_I2C 1
232 #define CONFIG_SYS_I2C_MODULE 1
233 #define CONFIG_SYS_I2C_SPEED 100000
234 #define CONFIG_SYS_I2C_SLAVE 0x7F
237 * EEPROM configuration
239 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
240 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
241 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
242 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
247 #if defined(CONFIG_DIGSY_REV5)
248 #define CONFIG_SYS_I2C_RTC_ADDR 0x56
249 #define CONFIG_RTC_RV3029
250 /* Enable 5k Ohm trickle charge resistor */
251 #define CONFIG_SYS_RV3029_TCR 0x20
253 #define CONFIG_RTC_DS1337
254 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
255 #define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
259 * Flash configuration
261 #define CONFIG_SYS_FLASH_CFI 1
262 #define CONFIG_FLASH_CFI_DRIVER 1
264 #if defined(CONFIG_DIGSY_REV5)
265 #define CONFIG_SYS_FLASH_BASE 0xFE000000
266 #define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000
267 #define CONFIG_SYS_MAX_FLASH_BANKS 2
268 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
269 CONFIG_SYS_FLASH_BASE_CS1}
270 #define CONFIG_SYS_UPDATE_FLASH_SIZE
271 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
273 #define CONFIG_SYS_FLASH_BASE 0xFF000000
274 #define CONFIG_SYS_MAX_FLASH_BANKS 1
275 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
278 #define CONFIG_SYS_MAX_FLASH_SECT 256
279 #define CONFIG_FLASH_16BIT
280 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
281 #define CONFIG_SYS_FLASH_SIZE 0x01000000
282 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000
283 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
285 #define OF_CPU "PowerPC,5200@0"
286 #define OF_SOC "soc5200@f0000000"
287 #define OF_TBCLK (bd->bi_busfreq / 4)
289 #define CONFIG_BOARD_EARLY_INIT_R
290 #define CONFIG_MISC_INIT_R
293 * Environment settings
295 #define CONFIG_ENV_IS_IN_FLASH 1
296 #if defined(CONFIG_LOWBOOT)
297 #define CONFIG_ENV_ADDR 0xFF060000
298 #else /* CONFIG_LOWBOOT */
299 #define CONFIG_ENV_ADDR 0xFFF60000
300 #endif /* CONFIG_LOWBOOT */
301 #define CONFIG_ENV_SIZE 0x10000
302 #define CONFIG_ENV_SECT_SIZE 0x20000
303 #define CONFIG_ENV_OVERWRITE 1
308 #define CONFIG_SYS_MBAR 0xF0000000
309 #define CONFIG_SYS_SDRAM_BASE 0x00000000
310 #if !defined(CONFIG_SYS_LOWBOOT)
311 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
313 #define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
317 * Use SRAM until RAM will be available
319 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
320 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
322 #define CONFIG_SYS_GBL_DATA_OFFSET \
323 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
324 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
326 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
327 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
328 #define CONFIG_SYS_RAMBOOT 1
331 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
332 #define CONFIG_SYS_MALLOC_LEN (4096 << 10)
333 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
336 * Ethernet configuration
338 #define CONFIG_MPC5xxx_FEC 1
339 #define CONFIG_MPC5xxx_FEC_MII100
340 #if defined(CONFIG_DIGSY_REV5)
341 #define CONFIG_PHY_ADDR 0x01
343 #define CONFIG_PHY_ADDR 0x00
345 #define CONFIG_PHY_RESET_DELAY 1000
347 #define CONFIG_NETCONSOLE /* include NetConsole support */
351 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
352 * Bit 0 (mask 0x80000000) : 0x1
353 * SPI on Tmr2/3/4/5 pins
354 * Bit 2:3 (mask 0x30000000) : 0x2
355 * ATA cs0/1 on csb_4/5
356 * Bit 6:7 (mask 0x03000000) : 0x2
357 * Ethernet 100Mbit with MD
358 * Bits 12:15 (mask 0x000f0000): 0x5
360 * Bits 18:19 (mask 0x00003000) : 0x2
361 * PSC3 - USB2 on PSC3
362 * Bits 20:23 (mask 0x00000f00) : 0x1
363 * PSC2 - CAN1&2 on PSC2 pins
364 * Bits 25:27 (mask 0x00000070) : 0x1
365 * PSC1 - AC97 functionality
366 * Bits 29:31 (mask 0x00000007) : 0x2
368 #define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
371 * Miscellaneous configurable options
373 #define CONFIG_SYS_LONGHELP
374 #define CONFIG_AUTO_COMPLETE 1
375 #define CONFIG_CMDLINE_EDITING 1
377 #define CONFIG_MX_CYCLIC 1
379 #define CONFIG_SYS_CBSIZE 1024
380 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
381 #define CONFIG_SYS_MAXARGS 32
382 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
384 #define CONFIG_SYS_ALT_MEMTEST
385 #define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
386 #define CONFIG_SYS_MEMTEST_START 0x00010000
387 #define CONFIG_SYS_MEMTEST_END 0x019fffff
389 #define CONFIG_SYS_LOAD_ADDR 0x00100000
392 * Various low-level settings
394 #define CONFIG_SYS_SDRAM_CS1 1
395 #define CONFIG_SYS_XLB_PIPELINING 1
397 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
398 #define CONFIG_SYS_HID0_FINAL HID0_ICE
400 #if defined(CONFIG_SYS_LOWBOOT)
401 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
402 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
403 #define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
406 #define CONFIG_SYS_CS4_START 0x60000000
407 #define CONFIG_SYS_CS4_SIZE 0x1000
408 #define CONFIG_SYS_CS4_CFG 0x0008FC00
410 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
411 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
412 #define CONFIG_SYS_CS0_CFG 0x0002DD00
414 #if defined(CONFIG_DIGSY_REV5)
415 #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1
416 #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
417 #define CONFIG_SYS_CS1_CFG 0x0002DD00
420 #define CONFIG_SYS_CS_BURST 0x00000000
421 #define CONFIG_SYS_CS_DEADCYCLE 0x11111111
423 #if !defined(CONFIG_SYS_LOWBOOT)
424 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
426 #define CONFIG_SYS_RESET_ADDRESS 0xff000100
432 #define CONFIG_USB_OHCI_NEW
433 #define CONFIG_SYS_OHCI_BE_CONTROLLER
435 #define CONFIG_USB_CLOCK 0x00013333
436 #define CONFIG_USB_CONFIG 0x00002000
438 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
439 #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
440 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
441 #define CONFIG_SYS_USB_OHCI_CPU_INIT
446 #define CONFIG_IDE_RESET
447 #define CONFIG_IDE_PREINIT
449 #define CONFIG_SYS_ATA_CS_ON_I2C2
450 #define CONFIG_SYS_IDE_MAXBUS 1
451 #define CONFIG_SYS_IDE_MAXDEVICE 1
453 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
454 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
455 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
456 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
457 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
458 #define CONFIG_SYS_ATA_STRIDE 4
460 #define CONFIG_ATAPI 1
461 #define CONFIG_LBA48 1
463 #endif /* __CONFIG_H */