Merge branch 'u-boot-arm/next' into 'u-boot-arm/master'
[platform/kernel/u-boot.git] / include / configs / digsy_mtc.h
1 /*
2  * (C) Copyright 2003-2004
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * (C) Copyright 2005-2007
6  * Modified for InterControl digsyMTC MPC5200 board by
7  * Frank Bodammer, GCD Hard- & Software GmbH,
8  *                 frank.bodammer@gcd-solutions.de
9  *
10  * (C) Copyright 2009 Semihalf
11  * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
12  *
13  * SPDX-License-Identifier:     GPL-2.0+
14  */
15
16 #ifndef __CONFIG_H
17 #define __CONFIG_H
18
19 /*
20  * High Level Configuration Options
21  */
22
23 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU */
24 #define CONFIG_DIGSY_MTC        1       /* ... on InterControl digsyMTC board */
25
26 /*
27  * Valid values for CONFIG_SYS_TEXT_BASE are:
28  * 0xFFF00000   boot high (standard configuration)
29  * 0xFE000000   boot low
30  * 0x00100000   boot from RAM (for testing only)
31  */
32 #ifndef CONFIG_SYS_TEXT_BASE
33 #define CONFIG_SYS_TEXT_BASE    0xFFF00000      /* Standard: boot high */
34 #endif
35
36 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000
37
38 #define CONFIG_SYS_CACHELINE_SIZE       32
39
40 /*
41  * Serial console configuration
42  */
43 #define CONFIG_PSC_CONSOLE      4       /* console is on PSC4  */
44 #define CONFIG_BAUDRATE         115200  /* ... at 115200  bps  */
45 #define CONFIG_SYS_BAUDRATE_TABLE       \
46         { 9600, 19200, 38400, 57600, 115200, 230400 }
47
48 /*
49  * PCI Mapping:
50  * 0x40000000 - 0x4fffffff - PCI Memory
51  * 0x50000000 - 0x50ffffff - PCI IO Space
52  */
53 #define CONFIG_PCI              1
54 #define CONFIG_PCI_PNP          1
55 #define CONFIG_PCI_SCAN_SHOW    1
56 #define CONFIG_PCI_BOOTDELAY    250
57
58 #define CONFIG_PCI_MEM_BUS      0x40000000
59 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
60 #define CONFIG_PCI_MEM_SIZE     0x10000000
61
62 #define CONFIG_PCI_IO_BUS       0x50000000
63 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
64 #define CONFIG_PCI_IO_SIZE      0x01000000
65
66 /*
67  *  Partitions
68  */
69 #define CONFIG_DOS_PARTITION
70 #define CONFIG_BZIP2
71
72 /*
73  * Video
74  */
75 #define CONFIG_VIDEO
76
77 #ifdef CONFIG_VIDEO
78 #define CONFIG_VIDEO_MB862xx
79 #define CONFIG_VIDEO_MB862xx_ACCEL
80 #define CONFIG_VIDEO_CORALP
81 #define CONFIG_CFB_CONSOLE
82 #define CONFIG_VIDEO_LOGO
83 #define CONFIG_VIDEO_BMP_LOGO
84 #define CONFIG_VIDEO_SW_CURSOR
85 #define CONFIG_VGA_AS_SINGLE_DEVICE
86 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
87 #define CONFIG_SPLASH_SCREEN
88 #define CONFIG_VIDEO_BMP_GZIP
89 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)       /* decompressed img */
90
91 /* Coral-PA clock frequency, geo and other both 133MHz */
92 #define CONFIG_SYS_MB862xx_CCF  0x00050000
93 /* Video SDRAM parameters */
94 #define CONFIG_SYS_MB862xx_MMR  0x11d7fa72
95 #endif
96
97 /*
98  * Command line configuration.
99  */
100 #include <config_cmd_default.h>
101
102 #ifdef CONFIG_VIDEO
103 #define CONFIG_CMD_BMP
104 #endif
105 #define CONFIG_CMD_CACHE
106 #define CONFIG_CMD_DATE
107 #define CONFIG_CMD_DHCP
108 #define CONFIG_CMD_DIAG
109 #define CONFIG_CMD_EEPROM
110 #define CONFIG_CMD_ELF
111 #define CONFIG_CMD_EXT2
112 #define CONFIG_CMD_FAT
113 #define CONFIG_CMD_I2C
114 #define CONFIG_CMD_IDE
115 #define CONFIG_CMD_IRQ
116 #define CONFIG_CMD_MII
117 #define CONFIG_CMD_PCI
118 #define CONFIG_CMD_PING
119 #define CONFIG_CMD_REGINFO
120 #define CONFIG_CMD_SAVES
121 #define CONFIG_CMD_SPI
122 #define CONFIG_CMD_USB
123
124 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
125 #define CONFIG_SYS_LOWBOOT      1
126 #endif
127
128 /*
129  * Autobooting
130  */
131 #define CONFIG_BOOTDELAY        1
132
133 #undef  CONFIG_BOOTARGS
134
135 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
136         "fw_image=digsyMPC.img\0"                                       \
137         "mtcb_start=mtc led diag orange; run mtcb_1\0"                  \
138         "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; "           \
139                 "do mtc led $x; done\0"                                 \
140         "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; "       \
141                 "else run mtcb_fw; fi\0"                                \
142         "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; "           \
143                 "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0"   \
144         "mtcb_update=mtc led user1 orange;"                             \
145                 "while mtc key; do ; done; run mtcb_2;\0"               \
146         "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0"     \
147         "mtcb_usb1=if fatload usb 0 400000 script.img; "                \
148                 "then run mtcb_doscript; else run mtcb_usb2; fi\0"      \
149         "mtcb_usb2=if fatload usb 0 400000 $fw_image; "                 \
150                 "then run mtcb_dousb; else run mtcb_ide; fi\0"          \
151         "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; "      \
152                 "run mtcb_wait_flickr mtcb_ds_1;\0"                     \
153         "mtcb_ds_1=if imi 400000; then mtc led usbbusy; "               \
154                 "source 400000; else run mtcb_error; fi\0"              \
155         "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0"     \
156         "mtcb_du_1=if imi 400000; then run mtcb_du_2; "                 \
157                 "else run mtcb_error; fi\0"                             \
158         "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; "         \
159                 "run mtcb_checkfw\0"                                    \
160         "mtcb_checkfw=if imi ff000000; then run mtcb_success; "         \
161                 "else run mtcb_error; fi\0"                             \
162         "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
163         "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0"            \
164         "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
165         "mtcb_uledflckr=mtc led user1 orange 11\0"                      \
166         "mtcb_error=mtc led user1 red\0"                                \
167         "mtcb_clear=erase ff000000 ff0fffff\0"                          \
168         "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0"                  \
169         "mtcb_success=mtc led user1 green\0"                            \
170         "mtcb_ide=if fatload ide 0 400000 $fw_image;"                   \
171                 "then run mtcb_doide; else run mtcb_error; fi\0"        \
172         "mtcb_doide=mtc led user2 green 1;"                             \
173                 "run mtcb_wait_flickr mtcb_di_1;\0"                     \
174         "mtcb_di_1=if imi 400000; then run mtcb_di_2;"                  \
175                 "else run mtcb_error; fi\0"                             \
176         "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0"        \
177         "ramdisk_num_sector=16\0"                                       \
178         "flash_base=ff000000\0"                                         \
179         "flashdisk_size=e00000\0"                                       \
180         "env_sector=fff60000\0"                                         \
181         "flashdisk_start=ff100000\0"                                    \
182         "load_cmd=tftp 400000 digsyMPC.img\0"                           \
183         "clear_cmd=erase ff000000 ff0fffff\0"                           \
184         "flash_cmd=cp.b 400000 ff000000 ${filesize}\0"                  \
185         "update_cmd=run load_cmd; "                                     \
186         "iminfo 400000; "                                               \
187         "run clear_cmd flash_cmd; "                                     \
188         "iminfo ff000000\0"                                             \
189         "spi_driver=yes\0"                                              \
190         "spi_watchdog=no\0"                                             \
191         "ftps_start=yes\0"                                              \
192         "ftps_user1=admin\0"                                            \
193         "ftps_pass1=admin\0"                                            \
194         "ftps_base1=/\0"                                                \
195         "ftps_home1=/\0"                                                \
196         "plc_sio_srv=no\0"                                              \
197         "plc_sio_baud=57600\0"                                          \
198         "plc_sio_parity=no\0"                                           \
199         "plc_sio_stop=1\0"                                              \
200         "plc_sio_com=2\0"                                               \
201         "plc_eth_srv=yes\0"                                             \
202         "plc_eth_port=1200\0"                                           \
203         "plc_root=/ide/\0"                                              \
204         "diag_level=0\0"                                                \
205         "webvisu=no\0"                                                  \
206         "plc_can1_routing=no\0"                                         \
207         "plc_can1_baudrate=250\0"                                       \
208         "plc_can2_routing=no\0"                                         \
209         "plc_can2_baudrate=250\0"                                       \
210         "plc_can3_routing=no\0"                                         \
211         "plc_can3_baudrate=250\0"                                       \
212         "plc_can4_routing=no\0"                                         \
213         "plc_can4_baudrate=250\0"                                       \
214         "netdev=eth0\0"                                                 \
215         "console=ttyPSC0\0"                                             \
216         "kernel_addr_r=400000\0"                                        \
217         "fdt_addr_r=600000\0"                                           \
218         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
219         "nfsroot=${serverip}:${rootpath}\0"                             \
220         "addip=setenv bootargs ${bootargs} "                            \
221         "ip=${ipaddr}:${serverip}:${gatewayip}:"                        \
222         "${netmask}:${hostname}:${netdev}:off panic=1\0"                \
223         "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
224         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
225         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
226                 "tftp ${fdt_addr_r} ${fdt_file};"                       \
227                 "run nfsargs addip addcons;"                            \
228                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
229         "load=tftp 200000 ${u-boot}\0"                                  \
230         "update=protect off FFF00000 +${filesize};"                     \
231                 "erase FFF00000 +${filesize};"                          \
232                 "cp.b 200000 FFF00000 ${filesize};"                     \
233                 "protect on FFF00000 +${filesize}\0"                    \
234         ""
235
236 #define CONFIG_BOOTCOMMAND      "run mtcb_start"
237
238 /*
239  * SPI configuration
240  */
241 #define CONFIG_HARD_SPI         1
242 #define CONFIG_MPC52XX_SPI      1
243
244 /*
245  * I2C configuration
246  */
247 #define CONFIG_HARD_I2C         1
248 #define CONFIG_SYS_I2C_MODULE   1
249 #define CONFIG_SYS_I2C_SPEED    100000
250 #define CONFIG_SYS_I2C_SLAVE    0x7F
251
252 /*
253  * EEPROM configuration
254  */
255 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
256 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
257 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
258 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
259
260 /*
261  * RTC configuration
262  */
263 #if defined(CONFIG_DIGSY_REV5)
264 #define CONFIG_SYS_I2C_RTC_ADDR 0x56
265 #define CONFIG_RTC_RV3029
266 /* Enable 5k Ohm trickle charge resistor */
267 #define CONFIG_SYS_RV3029_TCR   0x20
268 #else
269 #define CONFIG_RTC_DS1337
270 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
271 #define CONFIG_SYS_DS1339_TCR_VAL       0xAB    /* diode + 4k resistor */
272 #endif
273
274 /*
275  * Flash configuration
276  */
277 #define CONFIG_SYS_FLASH_CFI            1
278 #define CONFIG_FLASH_CFI_DRIVER 1
279
280 #if defined(CONFIG_DIGSY_REV5)
281 #define CONFIG_SYS_FLASH_BASE           0xFE000000
282 #define CONFIG_SYS_FLASH_BASE_CS1       0xFC000000
283 #define CONFIG_SYS_MAX_FLASH_BANKS      2
284 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, \
285                                         CONFIG_SYS_FLASH_BASE_CS1}
286 #define CONFIG_SYS_UPDATE_FLASH_SIZE
287 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
288 #else
289 #define CONFIG_SYS_FLASH_BASE           0xFF000000
290 #define CONFIG_SYS_MAX_FLASH_BANKS      1
291 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
292 #endif
293
294 #define CONFIG_SYS_MAX_FLASH_SECT       256
295 #define CONFIG_FLASH_16BIT
296 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
297 #define CONFIG_SYS_FLASH_SIZE   0x01000000
298 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000
299 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
300
301 #define CONFIG_OF_LIBFDT  1
302 #define CONFIG_OF_BOARD_SETUP   1
303
304 #define OF_CPU                  "PowerPC,5200@0"
305 #define OF_SOC                  "soc5200@f0000000"
306 #define OF_TBCLK                (bd->bi_busfreq / 4)
307
308 #define CONFIG_BOARD_EARLY_INIT_R
309 #define CONFIG_MISC_INIT_R
310
311 /*
312  * Environment settings
313  */
314 #define CONFIG_ENV_IS_IN_FLASH  1
315 #if defined(CONFIG_LOWBOOT)
316 #define CONFIG_ENV_ADDR         0xFF060000
317 #else   /* CONFIG_LOWBOOT */
318 #define CONFIG_ENV_ADDR         0xFFF60000
319 #endif  /* CONFIG_LOWBOOT */
320 #define CONFIG_ENV_SIZE         0x10000
321 #define CONFIG_ENV_SECT_SIZE    0x20000
322 #define CONFIG_ENV_OVERWRITE    1
323
324 /*
325  * Memory map
326  */
327 #define CONFIG_SYS_MBAR         0xF0000000
328 #define CONFIG_SYS_SDRAM_BASE           0x00000000
329 #if !defined(CONFIG_SYS_LOWBOOT)
330 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
331 #else
332 #define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
333 #endif
334
335 /*
336  *  Use SRAM until RAM will be available
337  */
338 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
339 #define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE
340
341 #define CONFIG_SYS_GBL_DATA_OFFSET      \
342         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
343 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
344
345 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
346 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
347 #define CONFIG_SYS_RAMBOOT              1
348 #endif
349
350 #define CONFIG_SYS_MONITOR_LEN  (256 << 10)
351 #define CONFIG_SYS_MALLOC_LEN   (4096 << 10)
352 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)
353
354 /*
355  * Ethernet configuration
356  */
357 #define CONFIG_MPC5xxx_FEC      1
358 #define CONFIG_MPC5xxx_FEC_MII100
359 #if defined(CONFIG_DIGSY_REV5)
360 #define CONFIG_PHY_ADDR         0x01
361 #else
362 #define CONFIG_PHY_ADDR         0x00
363 #endif
364 #define CONFIG_PHY_RESET_DELAY  1000
365
366 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
367
368 /*
369  * GPIO configuration
370  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
371  *  Bit 0   (mask 0x80000000) : 0x1
372  * SPI on Tmr2/3/4/5 pins
373  *  Bit 2:3 (mask 0x30000000) : 0x2
374  * ATA cs0/1 on csb_4/5
375  *  Bit 6:7 (mask 0x03000000) : 0x2
376  * Ethernet 100Mbit with MD
377  *  Bits 12:15 (mask 0x000f0000): 0x5
378  * USB - Two UARTs
379  *  Bits 18:19 (mask 0x00003000) : 0x2
380  * PSC3 - USB2 on PSC3
381  *  Bits 20:23 (mask 0x00000f00) : 0x1
382  * PSC2 - CAN1&2 on PSC2 pins
383  *  Bits 25:27 (mask 0x00000070) : 0x1
384  * PSC1 - AC97 functionality
385  *  Bits 29:31 (mask 0x00000007) : 0x2
386  */
387 #define CONFIG_SYS_GPS_PORT_CONFIG      0xA2552112
388
389 /*
390  * Miscellaneous configurable options
391  */
392 #define CONFIG_SYS_LONGHELP
393 #define CONFIG_AUTO_COMPLETE    1
394 #define CONFIG_CMDLINE_EDITING  1
395 #define CONFIG_SYS_HUSH_PARSER
396
397 #define CONFIG_AUTOBOOT_KEYED
398 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
399 #define CONFIG_AUTOBOOT_DELAY_STR       " "
400
401 #define CONFIG_LOOPW            1
402 #define CONFIG_MX_CYCLIC        1
403 #define CONFIG_ZERO_BOOTDELAY_CHECK
404
405 #define CONFIG_SYS_CBSIZE               1024
406 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
407 #define CONFIG_SYS_MAXARGS              32
408 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
409
410 #define CONFIG_SYS_ALT_MEMTEST
411 #define CONFIG_SYS_MEMTEST_SCRATCH      0x00001000
412 #define CONFIG_SYS_MEMTEST_START        0x00010000
413 #define CONFIG_SYS_MEMTEST_END          0x019fffff
414
415 #define CONFIG_SYS_LOAD_ADDR            0x00100000
416
417 /*
418  * Various low-level settings
419  */
420 #define CONFIG_SYS_SDRAM_CS1            1
421 #define CONFIG_SYS_XLB_PIPELINING       1
422
423 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
424 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
425
426 #if defined(CONFIG_SYS_LOWBOOT)
427 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
428 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
429 #define CONFIG_SYS_BOOTCS_CFG           0x0002DD00
430 #endif
431
432 #define CONFIG_SYS_CS4_START            0x60000000
433 #define CONFIG_SYS_CS4_SIZE             0x1000
434 #define CONFIG_SYS_CS4_CFG              0x0008FC00
435
436 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
437 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
438 #define CONFIG_SYS_CS0_CFG              0x0002DD00
439
440 #if defined(CONFIG_DIGSY_REV5)
441 #define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH_BASE_CS1
442 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_FLASH_SIZE
443 #define CONFIG_SYS_CS1_CFG              0x0002DD00
444 #endif
445
446 #define CONFIG_SYS_CS_BURST             0x00000000
447 #define CONFIG_SYS_CS_DEADCYCLE 0x11111111
448
449 #if !defined(CONFIG_SYS_LOWBOOT)
450 #define CONFIG_SYS_RESET_ADDRESS        0xfff00100
451 #else
452 #define CONFIG_SYS_RESET_ADDRESS        0xff000100
453 #endif
454
455 /*
456  * USB
457  */
458 #define CONFIG_USB_OHCI_NEW
459 #define CONFIG_SYS_OHCI_BE_CONTROLLER
460 #define CONFIG_USB_STORAGE
461
462 #define CONFIG_USB_CLOCK        0x00013333
463 #define CONFIG_USB_CONFIG       0x00002000
464
465 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
466 #define CONFIG_SYS_USB_OHCI_REGS_BASE   MPC5XXX_USB
467 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "mpc5200"
468 #define CONFIG_SYS_USB_OHCI_CPU_INIT
469
470 /*
471  * IDE/ATA
472  */
473 #define CONFIG_IDE_RESET
474 #define CONFIG_IDE_PREINIT
475
476 #define CONFIG_SYS_ATA_CS_ON_I2C2
477 #define CONFIG_SYS_IDE_MAXBUS           1
478 #define CONFIG_SYS_IDE_MAXDEVICE        1
479
480 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
481 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
482 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
483 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
484 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
485 #define CONFIG_SYS_ATA_STRIDE           4
486
487 #define CONFIG_ATAPI            1
488 #define CONFIG_LBA48            1
489
490 #endif /* __CONFIG_H */