2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
8 * Frederik Kriewitz <frederik@kriewitz.eu>
10 * Configuration settings for the DevKit8000 board.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 /* High Level Configuration Options */
35 #define CONFIG_OMAP 1 /* in a TI OMAP core */
36 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
37 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
38 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
39 #define CONFIG_OMAP_GPIO
42 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
43 * 64 bytes before this address should be set aside for u-boot.img's
44 * header. That is 0x800FFFC0--0x80100000 should not be used for any
47 #define CONFIG_SYS_TEXT_BASE 0x80100000
49 #define CONFIG_SDRC /* The chip has SDRC controller */
51 #include <asm/arch/cpu.h> /* get chip and board defs */
52 #include <asm/arch/omap3.h>
54 /* Display CPU and Board information */
55 #define CONFIG_DISPLAY_CPUINFO 1
56 #define CONFIG_DISPLAY_BOARDINFO 1
59 #define V_OSCK 26000000 /* Clock output from T2 */
60 #define V_SCLK (V_OSCK >> 1)
62 #define CONFIG_MISC_INIT_R
64 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
65 #define CONFIG_SETUP_MEMORY_TAGS 1
66 #define CONFIG_INITRD_TAG 1
67 #define CONFIG_REVISION_TAG 1
69 #define CONFIG_OF_LIBFDT 1
71 /* Size of malloc() pool */
72 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
74 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
76 /* Hardware drivers */
78 #define CONFIG_NET_RETRY_COUNT 20
79 #define CONFIG_DRIVER_DM9000 1
80 #define CONFIG_DM9000_BASE 0x2c000000
81 #define DM9000_IO CONFIG_DM9000_BASE
82 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
83 #define CONFIG_DM9000_USE_16BIT 1
84 #define CONFIG_DM9000_NO_SROM 1
85 #undef CONFIG_DM9000_DEBUG
87 /* NS16550 Configuration */
88 #define CONFIG_SYS_NS16550
89 #define CONFIG_SYS_NS16550_SERIAL
90 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
91 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
93 /* select serial console configuration */
94 #define CONFIG_CONS_INDEX 3
95 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
96 #define CONFIG_SERIAL3 3
97 #define CONFIG_BAUDRATE 115200
98 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
102 #define CONFIG_GENERIC_MMC 1
104 #define CONFIG_OMAP_HSMMC 1
105 #define CONFIG_DOS_PARTITION 1
108 #define CONFIG_HARD_I2C 1
109 #define CONFIG_SYS_I2C_SPEED 100000
110 #define CONFIG_SYS_I2C_SLAVE 1
111 #define CONFIG_SYS_I2C_BUS 0
112 #define CONFIG_SYS_I2C_BUS_SELECT 1
113 #define CONFIG_DRIVER_OMAP34XX_I2C 1
116 #define CONFIG_TWL4030_POWER 1
117 #define CONFIG_TWL4030_LED 1
119 /* Board NAND Info */
120 #define CONFIG_SYS_NO_FLASH /* no NOR flash */
121 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
122 #define MTDIDS_DEFAULT "nand0=nand"
123 #define MTDPARTS_DEFAULT "mtdparts=nand:" \
126 "128k(u-boot-env)," \
130 #define CONFIG_NAND_OMAP_GPMC
131 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
133 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
134 /* to access nand at */
136 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
138 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
140 #define CONFIG_JFFS2_NAND
141 /* nand device jffs2 lives on */
142 #define CONFIG_JFFS2_DEV "nand0"
143 /* start of jffs2 partition */
144 #define CONFIG_JFFS2_PART_OFFSET 0x680000
145 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
148 /* commands to include */
149 #include <config_cmd_default.h>
151 #define CONFIG_CMD_DHCP /* DHCP support */
152 #define CONFIG_CMD_EXT2 /* EXT2 Support */
153 #define CONFIG_CMD_FAT /* FAT support */
154 #define CONFIG_CMD_I2C /* I2C serial bus support */
155 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
156 #define CONFIG_CMD_MMC /* MMC support */
157 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
158 #define CONFIG_CMD_NAND /* NAND support */
159 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
161 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
162 #undef CONFIG_CMD_IMI /* iminfo */
164 /* BOOTP/DHCP options */
165 #define CONFIG_BOOTP_SUBNETMASK
166 #define CONFIG_BOOTP_GATEWAY
167 #define CONFIG_BOOTP_HOSTNAME
168 #define CONFIG_BOOTP_NISDOMAIN
169 #define CONFIG_BOOTP_BOOTPATH
170 #define CONFIG_BOOTP_BOOTFILESIZE
171 #define CONFIG_BOOTP_DNS
172 #define CONFIG_BOOTP_DNS2
173 #define CONFIG_BOOTP_SEND_HOSTNAME
174 #define CONFIG_BOOTP_NTPSERVER
175 #define CONFIG_BOOTP_TIMEOFFSET
176 #undef CONFIG_BOOTP_VENDOREX
178 /* Environment information */
179 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
181 #define CONFIG_BOOTDELAY 3
183 #define CONFIG_EXTRA_ENV_SETTINGS \
184 "loadaddr=0x82000000\0" \
185 "console=ttyO2,115200n8\0" \
188 "dvimode=1024x768MR-16@60\0" \
189 "defaultdisplay=dvi\0" \
190 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
193 "setenv bootargs console=${console} " \
195 "omapfb.mode=dvi:${dvimode} " \
196 "omapdss.def_disp=${defaultdisplay}\0" \
199 "setenv bootargs ${bootargs} " \
200 "root=/dev/mmcblk0p2 " \
204 "setenv bootargs ${bootargs} " \
205 "omapfb.mode=dvi:${dvimode} " \
206 "omapdss.def_disp=${defaultdisplay} " \
207 "root=/dev/mtdblock4 " \
208 "rootfstype=jffs2 " \
212 "setenv bootargs ${bootargs} " \
214 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
215 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
218 "dnsip2=${dnsip2}\0" \
219 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
220 "bootscript=echo Running bootscript from mmc ...; " \
221 "source ${loadaddr}\0" \
222 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
223 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
224 "mmcboot=echo Booting from mmc ...; " \
226 "bootm ${loadaddr}\0" \
227 "nandboot=echo Booting from nand ...; " \
229 "nand read ${loadaddr} 280000 400000; " \
230 "bootm ${loadaddr}\0" \
231 "netboot=echo Booting from network ...; " \
232 "dhcp ${loadaddr}; " \
234 "bootm ${loadaddr}\0" \
235 "autoboot=if mmc rescan ${mmcdev}; then " \
236 "if run loadbootscript; then " \
239 "if run loaduimage; then " \
241 "else run nandboot; " \
244 "else run nandboot; fi\0"
247 #define CONFIG_BOOTCOMMAND "run autoboot"
249 /* Miscellaneous configurable options */
250 #define CONFIG_SYS_LONGHELP /* undef to save memory */
251 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
252 #define CONFIG_AUTO_COMPLETE 1
253 #define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
254 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
255 /* Print Buffer Size */
256 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
257 sizeof(CONFIG_SYS_PROMPT) + 16)
258 #define CONFIG_SYS_MAXARGS 128 /* max number of command args */
260 /* Boot Argument Buffer Size */
261 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
263 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
264 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
265 0x01000000) /* 16MB */
267 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
270 * OMAP3 has 12 GP timers, they can be driven by the system clock
271 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
272 * This rate is divided by a local divisor.
274 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
275 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
276 #define CONFIG_SYS_HZ 1000
278 /* Physical Memory Map */
279 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
280 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
281 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
283 /* NAND and environment organization */
284 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
286 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
288 #define CONFIG_ENV_IS_IN_NAND 1
289 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
291 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
293 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
294 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
295 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
296 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
297 CONFIG_SYS_INIT_RAM_SIZE - \
298 GENERATED_GBL_DATA_SIZE)
301 #define CONFIG_SYS_SRAM_START 0x40200000
302 #define CONFIG_SYS_SRAM_SIZE 0x10000
304 /* Defines for SPL */
306 #define CONFIG_SPL_NAND_SIMPLE
308 #define CONFIG_SPL_LIBCOMMON_SUPPORT
309 #define CONFIG_SPL_LIBDISK_SUPPORT
310 #define CONFIG_SPL_BOARD_INIT
311 #define CONFIG_SPL_I2C_SUPPORT
312 #define CONFIG_SPL_LIBGENERIC_SUPPORT
313 #define CONFIG_SPL_SERIAL_SUPPORT
314 #define CONFIG_SPL_GPIO_SUPPORT
315 #define CONFIG_SPL_POWER_SUPPORT
316 #define CONFIG_SPL_NAND_SUPPORT
317 #define CONFIG_SPL_MMC_SUPPORT
318 #define CONFIG_SPL_FAT_SUPPORT
319 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
320 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
321 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
322 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
324 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
325 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
326 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
328 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
329 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
331 /* NAND boot config */
332 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
333 #define CONFIG_SYS_NAND_PAGE_COUNT 64
334 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
335 #define CONFIG_SYS_NAND_OOBSIZE 64
336 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
337 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
338 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
341 #define CONFIG_SYS_NAND_ECCSIZE 512
342 #define CONFIG_SYS_NAND_ECCBYTES 3
344 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
346 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
347 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
349 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
350 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
352 /* SPL OS boot options */
353 #define CONFIG_SPL_OS_BOOT
354 #define CONFIG_SPL_OS_BOOT_KEY 26
356 #define CONFIG_CMD_SPL
357 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
358 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
360 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
361 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
363 #endif /* __CONFIG_H */