2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
8 * Frederik Kriewitz <frederik@kriewitz.eu>
10 * Configuration settings for the DevKit8000 board.
12 * SPDX-License-Identifier: GPL-2.0+
18 /* High Level Configuration Options */
19 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
20 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
23 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
24 * 64 bytes before this address should be set aside for u-boot.img's
25 * header. That is 0x800FFFC0--0x80100000 should not be used for any
28 #define CONFIG_SYS_TEXT_BASE 0x80100000
30 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
31 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
33 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
34 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
38 /* Physical Memory Map */
39 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
41 #include <configs/ti_omap3_common.h>
43 #define CONFIG_MISC_INIT_R
45 #define CONFIG_REVISION_TAG 1
47 /* Size of malloc() pool */
48 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
50 #undef CONFIG_SYS_MALLOC_LEN
51 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
53 /* Hardware drivers */
55 #define CONFIG_NET_RETRY_COUNT 20
56 #define CONFIG_DRIVER_DM9000 1
57 #define CONFIG_DM9000_BASE 0x2c000000
58 #define DM9000_IO CONFIG_DM9000_BASE
59 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
60 #define CONFIG_DM9000_USE_16BIT 1
61 #define CONFIG_DM9000_NO_SROM 1
62 #undef CONFIG_DM9000_DEBUG
66 #undef CONFIG_OMAP3_SPI
69 #undef CONFIG_SYS_I2C_OMAP24XX
70 #define CONFIG_SYS_I2C_OMAP34XX
73 #define CONFIG_TWL4030_LED 1
76 #define MTDIDS_DEFAULT "nand0=nand"
77 #define MTDPARTS_DEFAULT "mtdparts=nand:" \
84 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
86 #define CONFIG_JFFS2_NAND
87 /* nand device jffs2 lives on */
88 #define CONFIG_JFFS2_DEV "nand0"
89 /* start of jffs2 partition */
90 #define CONFIG_JFFS2_PART_OFFSET 0x680000
91 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
94 /* commands to include */
95 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
96 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
98 #undef CONFIG_SUPPORT_RAW_INITRD
99 #undef CONFIG_FAT_WRITE
101 /* BOOTP/DHCP options */
102 #define CONFIG_BOOTP_SUBNETMASK
103 #define CONFIG_BOOTP_GATEWAY
104 #define CONFIG_BOOTP_HOSTNAME
105 #define CONFIG_BOOTP_NISDOMAIN
106 #define CONFIG_BOOTP_BOOTPATH
107 #define CONFIG_BOOTP_BOOTFILESIZE
108 #define CONFIG_BOOTP_DNS
109 #define CONFIG_BOOTP_DNS2
110 #define CONFIG_BOOTP_SEND_HOSTNAME
111 #define CONFIG_BOOTP_NTPSERVER
112 #define CONFIG_BOOTP_TIMEOFFSET
113 #undef CONFIG_BOOTP_VENDOREX
115 /* Environment information */
116 #define CONFIG_EXTRA_ENV_SETTINGS \
117 "loadaddr=0x82000000\0" \
118 "console=ttyO2,115200n8\0" \
121 "dvimode=1024x768MR-16@60\0" \
122 "defaultdisplay=dvi\0" \
123 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
126 "setenv bootargs console=${console} " \
128 "omapfb.mode=dvi:${dvimode} " \
129 "omapdss.def_disp=${defaultdisplay}\0" \
132 "setenv bootargs ${bootargs} " \
133 "root=/dev/mmcblk0p2 " \
138 "setenv bootargs ${bootargs} " \
139 "omapfb.mode=dvi:${dvimode} " \
140 "omapdss.def_disp=${defaultdisplay} " \
141 "root=/dev/mtdblock4 " \
142 "rootfstype=jffs2 " \
146 "setenv bootargs ${bootargs} " \
148 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
149 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
152 "dnsip2=${dnsip2}\0" \
153 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
154 "bootscript=echo Running bootscript from mmc ...; " \
155 "source ${loadaddr}\0" \
156 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
157 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
158 "mmcboot=echo Booting from mmc ...; " \
160 "bootm ${loadaddr}\0" \
161 "nandboot=echo Booting from nand ...; " \
163 "nand read ${loadaddr} 280000 400000; " \
164 "bootm ${loadaddr}\0" \
165 "netboot=echo Booting from network ...; " \
166 "dhcp ${loadaddr}; " \
168 "bootm ${loadaddr}\0" \
169 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
170 "if run loadbootscript; then " \
173 "if run loaduimage; then " \
175 "else run nandboot; " \
178 "else run nandboot; fi\0"
180 #define CONFIG_BOOTCOMMAND "run autoboot"
182 /* Boot Argument Buffer Size */
183 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
184 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
185 0x01000000) /* 16MB */
187 /* NAND and environment organization */
188 #define CONFIG_ENV_IS_IN_NAND 1
189 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
191 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
194 #define CONFIG_SYS_SRAM_START 0x40200000
195 #define CONFIG_SYS_SRAM_SIZE 0x10000
197 /* Defines for SPL */
199 #undef CONFIG_SPL_TEXT_BASE
200 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
202 /* NAND boot config */
203 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
204 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
205 #define CONFIG_SYS_NAND_PAGE_COUNT 64
206 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
207 #define CONFIG_SYS_NAND_OOBSIZE 64
208 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
209 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
210 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
213 #define CONFIG_SYS_NAND_ECCSIZE 512
214 #define CONFIG_SYS_NAND_ECCBYTES 3
215 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
217 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
218 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
220 /* SPL OS boot options */
221 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
222 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
224 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
226 #undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
227 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
228 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
229 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
230 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
231 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
233 #undef CONFIG_SYS_SPL_ARGS_ADDR
234 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
236 #endif /* __CONFIG_H */