include/configs/devkit8000.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Texas Instruments.
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  * Syed Mohammed Khasim <x0khasim@ti.com>
   6  *
   7  * (C) Copyright 2009
   8  * Frederik Kriewitz <frederik@kriewitz.eu>
   9  *
  10  * Configuration settings for the DevKit8000 board.
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /* High Level Configuration Options */
  19 #define CONFIG_OMAP             1       /* in a TI OMAP core */
  20 #define CONFIG_OMAP34XX         1       /* which is a 34XX */
  21 #define CONFIG_OMAP3_DEVKIT8000 1       /* working with DevKit8000 */
  22 #define CONFIG_MACH_TYPE        MACH_TYPE_DEVKIT8000
  23 #define CONFIG_OMAP_GPIO
  24 #define CONFIG_OMAP_COMMON
  25
  26 /*
  27  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  28  * 64 bytes before this address should be set aside for u-boot.img's
  29  * header. That is 0x800FFFC0--0x80100000 should not be used for any
  30  * other needs.
  31  */
  32 #define CONFIG_SYS_TEXT_BASE    0x80100000
  33
  34 #define CONFIG_SDRC     /* The chip has SDRC controller */
  35
  36 #include <asm/arch/cpu.h>               /* get chip and board defs */
  37 #include <asm/arch/omap3.h>
  38
  39 /* Display CPU and Board information */
  40 #define CONFIG_DISPLAY_CPUINFO          1
  41 #define CONFIG_DISPLAY_BOARDINFO        1
  42
  43 /* Clock Defines */
  44 #define V_OSCK                          26000000        /* Clock output from T2 */
  45 #define V_SCLK                          (V_OSCK >> 1)
  46
  47 #define CONFIG_MISC_INIT_R
  48
  49 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  50 #define CONFIG_SETUP_MEMORY_TAGS        1
  51 #define CONFIG_INITRD_TAG               1
  52 #define CONFIG_REVISION_TAG             1
  53
  54 #define CONFIG_OF_LIBFDT                1
  55
  56 /* Size of malloc() pool */
  57 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB */
  58                                                 /* Sector */
  59 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  60
  61 /* Hardware drivers */
  62 /* DM9000 */
  63 #define CONFIG_NET_RETRY_COUNT          20
  64 #define CONFIG_DRIVER_DM9000            1
  65 #define CONFIG_DM9000_BASE              0x2c000000
  66 #define DM9000_IO                       CONFIG_DM9000_BASE
  67 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 0x400)
  68 #define CONFIG_DM9000_USE_16BIT         1
  69 #define CONFIG_DM9000_NO_SROM           1
  70 #undef  CONFIG_DM9000_DEBUG
  71
  72 /* NS16550 Configuration */
  73 #define CONFIG_SYS_NS16550
  74 #define CONFIG_SYS_NS16550_SERIAL
  75 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  76 #define CONFIG_SYS_NS16550_CLK          48000000 /* 48MHz (APLL96/2) */
  77
  78 /* select serial console configuration */
  79 #define CONFIG_CONS_INDEX               3
  80 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  81 #define CONFIG_SERIAL3                  3
  82 #define CONFIG_BAUDRATE                 115200
  83 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  84                                         115200}
  85
  86 /* MMC */
  87 #define CONFIG_GENERIC_MMC              1
  88 #define CONFIG_MMC                      1
  89 #define CONFIG_OMAP_HSMMC               1
  90 #define CONFIG_DOS_PARTITION            1
  91
  92 /* I2C */
  93 #define CONFIG_SYS_I2C
  94 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
  95 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
  96 #define CONFIG_SYS_I2C_OMAP34XX
  97
  98 /* TWL4030 */
  99 #define CONFIG_TWL4030_POWER            1
 100 #define CONFIG_TWL4030_LED              1
 101
 102 /* Board NAND Info */
 103 #define CONFIG_SYS_NO_FLASH             /* no NOR flash */
 104 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 105 #define MTDIDS_DEFAULT                  "nand0=nand"
 106 #define MTDPARTS_DEFAULT                "mtdparts=nand:" \
 107                                                 "512k(x-loader)," \
 108                                                 "1920k(u-boot)," \
 109                                                 "128k(u-boot-env)," \
 110                                                 "4m(kernel)," \
 111                                                 "-(fs)"
 112
 113 #define CONFIG_NAND_OMAP_GPMC
 114 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 115                                                         /* to access nand */
 116 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 117                                                         /* to access nand at */
 118                                                         /* CS0 */
 119 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 120                                                         /* devices */
 121 #define CONFIG_JFFS2_NAND
 122 /* nand device jffs2 lives on */
 123 #define CONFIG_JFFS2_DEV                "nand0"
 124 /* start of jffs2 partition */
 125 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 126 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* size of jffs2 */
 127                                                         /* partition */
 128
 129 /* commands to include */
 130 #include <config_cmd_default.h>
 131
 132 #define CONFIG_CMD_DHCP                 /* DHCP support                 */
 133 #define CONFIG_CMD_EXT2                 /* EXT2 Support                 */
 134 #define CONFIG_CMD_FAT                  /* FAT support                  */
 135 #define CONFIG_CMD_I2C                  /* I2C serial bus support       */
 136 #define CONFIG_CMD_JFFS2                /* JFFS2 Support                */
 137 #define CONFIG_CMD_MMC                  /* MMC support                  */
 138 #define CONFIG_CMD_MTDPARTS             /* Enable MTD parts commands    */
 139 #define CONFIG_CMD_NAND                 /* NAND support                 */
 140 #define CONFIG_CMD_NAND_LOCK_UNLOCK     /* nand (un)lock commands       */
 141
 142 #undef CONFIG_CMD_FPGA                  /* FPGA configuration Support   */
 143 #undef CONFIG_CMD_IMI                   /* iminfo                       */
 144
 145 /* BOOTP/DHCP options */
 146 #define CONFIG_BOOTP_SUBNETMASK
 147 #define CONFIG_BOOTP_GATEWAY
 148 #define CONFIG_BOOTP_HOSTNAME
 149 #define CONFIG_BOOTP_NISDOMAIN
 150 #define CONFIG_BOOTP_BOOTPATH
 151 #define CONFIG_BOOTP_BOOTFILESIZE
 152 #define CONFIG_BOOTP_DNS
 153 #define CONFIG_BOOTP_DNS2
 154 #define CONFIG_BOOTP_SEND_HOSTNAME
 155 #define CONFIG_BOOTP_NTPSERVER
 156 #define CONFIG_BOOTP_TIMEOFFSET
 157 #undef CONFIG_BOOTP_VENDOREX
 158
 159 /* Environment information */
 160 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
 161
 162 #define CONFIG_BOOTDELAY                3
 163
 164 #define CONFIG_EXTRA_ENV_SETTINGS \
 165         "loadaddr=0x82000000\0" \
 166         "console=ttyO2,115200n8\0" \
 167         "mmcdev=0\0" \
 168         "vram=12M\0" \
 169         "dvimode=1024x768MR-16@60\0" \
 170         "defaultdisplay=dvi\0" \
 171         "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
 172         "kernelopts=rw\0" \
 173         "commonargs=" \
 174                 "setenv bootargs console=${console} " \
 175                 "vram=${vram} " \
 176                 "omapfb.mode=dvi:${dvimode} " \
 177                 "omapdss.def_disp=${defaultdisplay}\0" \
 178         "mmcargs=" \
 179                 "run commonargs; " \
 180                 "setenv bootargs ${bootargs} " \
 181                 "root=/dev/mmcblk0p2 " \
 182                 "rootwait " \
 183                 "${kernelopts}\0" \
 184         "nandargs=" \
 185                 "run commonargs; " \
 186                 "setenv bootargs ${bootargs} " \
 187                 "omapfb.mode=dvi:${dvimode} " \
 188                 "omapdss.def_disp=${defaultdisplay} " \
 189                 "root=/dev/mtdblock4 " \
 190                 "rootfstype=jffs2 " \
 191                 "${kernelopts}\0" \
 192         "netargs=" \
 193                 "run commonargs; " \
 194                 "setenv bootargs ${bootargs} " \
 195                 "root=/dev/nfs " \
 196                 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
 197                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
 198                 "${kernelopts} " \
 199                 "dnsip1=${dnsip} " \
 200                 "dnsip2=${dnsip2}\0" \
 201         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 202         "bootscript=echo Running bootscript from mmc ...; " \
 203                 "source ${loadaddr}\0" \
 204         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 205         "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
 206         "mmcboot=echo Booting from mmc ...; " \
 207                 "run mmcargs; " \
 208                 "bootm ${loadaddr}\0" \
 209         "nandboot=echo Booting from nand ...; " \
 210                 "run nandargs; " \
 211                 "nand read ${loadaddr} 280000 400000; " \
 212                 "bootm ${loadaddr}\0" \
 213         "netboot=echo Booting from network ...; " \
 214                 "dhcp ${loadaddr}; " \
 215                 "run netargs; " \
 216                 "bootm ${loadaddr}\0" \
 217         "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
 218                         "if run loadbootscript; then " \
 219                                 "run bootscript; " \
 220                         "else " \
 221                                 "if run loaduimage; then " \
 222                                         "run mmcboot; " \
 223                                 "else run nandboot; " \
 224                                 "fi; " \
 225                         "fi; " \
 226                 "else run nandboot; fi\0"
 227
 228
 229 #define CONFIG_BOOTCOMMAND "run autoboot"
 230
 231 /* Miscellaneous configurable options */
 232 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 233 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 234 #define CONFIG_AUTO_COMPLETE            1
 235 #define CONFIG_SYS_PROMPT               "OMAP3 DevKit8000 # "
 236 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 237 /* Print Buffer Size */
 238 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 239                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 240 #define CONFIG_SYS_MAXARGS              128     /* max number of command args */
 241
 242 /* Boot Argument Buffer Size */
 243 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 244
 245 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0 + 0x07000000)
 246 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 247                                         0x01000000) /* 16MB */
 248
 249 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0 + 0x02000000)
 250
 251 /*
 252  * OMAP3 has 12 GP timers, they can be driven by the system clock
 253  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 254  * This rate is divided by a local divisor.
 255  */
 256 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 257 #define CONFIG_SYS_PTV                  2 /* Divisor: 2^(PTV+1) => 8 */
 258
 259 /*  Physical Memory Map  */
 260 #define CONFIG_NR_DRAM_BANKS            2 /* CS1 may or may not be populated */
 261 #define PHYS_SDRAM_1                    OMAP34XX_SDRC_CS0
 262 #define PHYS_SDRAM_2                    OMAP34XX_SDRC_CS1
 263
 264 /* NAND and environment organization  */
 265 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 266
 267 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 268
 269 #define CONFIG_ENV_IS_IN_NAND           1
 270 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 271
 272 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 273
 274 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
 275 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 276 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 277 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 278                                                          CONFIG_SYS_INIT_RAM_SIZE - \
 279                                                          GENERATED_GBL_DATA_SIZE)
 280
 281 /* SRAM config */
 282 #define CONFIG_SYS_SRAM_START              0x40200000
 283 #define CONFIG_SYS_SRAM_SIZE               0x10000
 284
 285 /* Defines for SPL */
 286 #define CONFIG_SPL
 287 #define CONFIG_SPL_FRAMEWORK
 288 #define CONFIG_SPL_NAND_SIMPLE
 289
 290 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 291 #define CONFIG_SPL_LIBDISK_SUPPORT
 292 #define CONFIG_SPL_BOARD_INIT
 293 #define CONFIG_SPL_I2C_SUPPORT
 294 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 295 #define CONFIG_SPL_SERIAL_SUPPORT
 296 #define CONFIG_SPL_GPIO_SUPPORT
 297 #define CONFIG_SPL_POWER_SUPPORT
 298 #define CONFIG_SPL_NAND_SUPPORT
 299 #define CONFIG_SPL_NAND_BASE
 300 #define CONFIG_SPL_NAND_DRIVERS
 301 #define CONFIG_SPL_NAND_ECC
 302 #define CONFIG_SPL_MMC_SUPPORT
 303 #define CONFIG_SPL_FAT_SUPPORT
 304 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
 305 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
 306 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
 307 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 308
 309 #define CONFIG_SPL_TEXT_BASE            0x40200000 /*CONFIG_SYS_SRAM_START*/
 310 #define CONFIG_SPL_MAX_SIZE             (54 * 1024)     /* 8 KB for stack */
 311 #define CONFIG_SPL_STACK                LOW_LEVEL_SRAM_STACK
 312
 313 #define CONFIG_SPL_BSS_START_ADDR       0x80000500 /* leave space for bootargs*/
 314 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 315
 316 /* NAND boot config */
 317 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT  16
 318 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 319 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 320 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 321 #define CONFIG_SYS_NAND_OOBSIZE         64
 322 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 323 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 324 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 325                                                 10, 11, 12, 13}
 326
 327 #define CONFIG_SYS_NAND_ECCSIZE         512
 328 #define CONFIG_SYS_NAND_ECCBYTES        3
 329 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 330
 331 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 332
 333 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 334 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x200000
 335
 336 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 337 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000        /* 1 MB */
 338
 339 /* SPL OS boot options */
 340 #define CONFIG_SPL_OS_BOOT
 341
 342 #define CONFIG_CMD_SPL
 343 #define CONFIG_CMD_SPL_WRITE_SIZE       0x400 /* 1024 byte */
 344 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
 345                                         0x400000)
 346 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
 347
 348 #define CONFIG_SPL_FAT_LOAD_KERNEL_NAME         "uImage"
 349 #define CONFIG_SPL_FAT_LOAD_ARGS_NAME           "args"
 350
 351 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
 352 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR   0x8   /* address 0x1000 */
 353 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS  8     /* 4KB */
 354
 355 #define CONFIG_SYS_SPL_ARGS_ADDR        (PHYS_SDRAM_1 + 0x100)
 356
 357 #endif /* __CONFIG_H */