1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Embest/Timll DevKit3250 board configuration file
5 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
8 #ifndef __CONFIG_DEVKIT3250_H__
9 #define __CONFIG_DEVKIT3250_H__
11 /* SoC and board defines */
12 #include <linux/sizes.h>
13 #include <asm/arch/cpu.h>
15 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250
18 * Memory configurations
20 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
21 #define CONFIG_SYS_SDRAM_SIZE SZ_64M
23 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
24 - GENERATED_GBL_DATA_SIZE)
29 #if !defined(CONFIG_SPL_BUILD)
30 #define CONFIG_DMA_LPC32XX
36 #define CONFIG_LPC32XX_GPIO
42 #define CONFIG_LPC32XX_ETH
43 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
48 #define CONFIG_SYS_MAX_FLASH_BANKS 1
49 #define CONFIG_SYS_MAX_FLASH_SECT 71
50 #define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE
51 #define CONFIG_SYS_FLASH_SIZE SZ_4M
56 #define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
57 #define CONFIG_SYS_MAX_NAND_DEVICE 1
58 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
63 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14
64 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666
65 #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000
66 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000
67 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14
68 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666
69 #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000
70 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000
72 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
73 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
78 #define CONFIG_USB_OHCI_LPC32XX
79 #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d
82 * U-Boot General Configurations
84 #define CONFIG_SYS_CBSIZE 1024
85 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
88 * Pass open firmware flat tree
95 #define CONFIG_BOOTCOMMAND \
97 "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \
98 "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \
99 "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \
100 "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \
101 "bootm ${loadaddr} - ${dtbaddr}"
103 #define CONFIG_EXTRA_ENV_SETTINGS \
105 "ethaddr=00:01:90:00:C0:81\0" \
106 "dtbaddr=0x81000000\0" \
107 "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \
108 "tftpdir=vladimir/oe/devkit3250\0" \
109 "userargs=oops=panic\0"
118 #define CONFIG_CMDLINE_TAG
119 #define CONFIG_SETUP_MEMORY_TAGS
121 #define CONFIG_BOOTFILE "uImage"
124 * SPL specific defines
126 /* SPL will be executed at offset 0 */
128 /* SPL will use SRAM as stack */
129 #define CONFIG_SPL_STACK 0x0000FFF8
131 /* Use the framework and generic lib */
133 /* SPL will use serial */
135 /* SPL loads an image from NAND */
136 #define CONFIG_SPL_NAND_RAW_ONLY
138 #define CONFIG_SPL_NAND_SOFTECC
140 #define CONFIG_SPL_MAX_SIZE 0x20000
141 #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
143 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
144 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
145 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
147 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
148 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
150 /* See common/spl/spl.c spl_set_header_raw_uboot() */
151 #define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE
154 * Include SoC specific configuration
156 #include <asm/arch/config.h>
158 #endif /* __CONFIG_DEVKIT3250_H__*/