include/configs/devkit3250.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Embest/Timll DevKit3250 board configuration file
   4  *
   5  * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
   6  */
   7
   8 #ifndef __CONFIG_DEVKIT3250_H__
   9 #define __CONFIG_DEVKIT3250_H__
  10
  11 /* SoC and board defines */
  12 #include <linux/sizes.h>
  13 #include <asm/arch/cpu.h>
  14
  15 #define CONFIG_MACH_TYPE                MACH_TYPE_DEVKIT3250
  16
  17 #if !defined(CONFIG_SPL_BUILD)
  18 #define CONFIG_SKIP_LOWLEVEL_INIT
  19 #endif
  20
  21 /*
  22  * Memory configurations
  23  */
  24 #define CONFIG_SYS_MALLOC_LEN           SZ_1M
  25 #define CONFIG_SYS_SDRAM_BASE           EMC_DYCS0_BASE
  26 #define CONFIG_SYS_SDRAM_SIZE           SZ_64M
  27
  28 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  29
  30 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_4K \
  31                                          - GENERATED_GBL_DATA_SIZE)
  32
  33 /*
  34  * Serial Driver
  35  */
  36 #define CONFIG_SYS_LPC32XX_UART         5   /* UART5 */
  37
  38 /*
  39  * DMA
  40  */
  41 #if !defined(CONFIG_SPL_BUILD)
  42 #define CONFIG_DMA_LPC32XX
  43 #endif
  44
  45 /*
  46  * I2C
  47  */
  48 #define CONFIG_SYS_I2C
  49 #define CONFIG_SYS_I2C_LPC32XX
  50 #define CONFIG_SYS_I2C_SPEED            100000
  51
  52 /*
  53  * GPIO
  54  */
  55 #define CONFIG_LPC32XX_GPIO
  56
  57 /*
  58  * Ethernet
  59  */
  60 #define CONFIG_RMII
  61 #define CONFIG_LPC32XX_ETH
  62 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  63
  64 /*
  65  * NOR Flash
  66  */
  67 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  68 #define CONFIG_SYS_MAX_FLASH_SECT       71
  69 #define CONFIG_SYS_FLASH_BASE           EMC_CS0_BASE
  70 #define CONFIG_SYS_FLASH_SIZE           SZ_4M
  71
  72 /*
  73  * NAND controller
  74  */
  75 #define CONFIG_SYS_NAND_BASE            SLC_NAND_BASE
  76 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  77 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  78
  79 /*
  80  * NAND chip timings
  81  */
  82 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS        14
  83 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH          66666666
  84 #define CONFIG_LPC32XX_NAND_SLC_WHOLD           200000000
  85 #define CONFIG_LPC32XX_NAND_SLC_WSETUP          50000000
  86 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS        14
  87 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH          66666666
  88 #define CONFIG_LPC32XX_NAND_SLC_RHOLD           200000000
  89 #define CONFIG_LPC32XX_NAND_SLC_RSETUP          50000000
  90
  91 #define CONFIG_SYS_NAND_BLOCK_SIZE              0x20000
  92 #define CONFIG_SYS_NAND_PAGE_SIZE               NAND_LARGE_BLOCK_PAGE_SIZE
  93
  94 /*
  95  * USB
  96  */
  97 #define CONFIG_USB_OHCI_LPC32XX
  98 #define CONFIG_USB_ISP1301_I2C_ADDR             0x2d
  99
 100 /*
 101  * U-Boot General Configurations
 102  */
 103 #define CONFIG_SYS_CBSIZE               1024
 104 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 105
 106 /*
 107  * Pass open firmware flat tree
 108  */
 109
 110 /*
 111  * Environment
 112  */
 113
 114 #define CONFIG_BOOTCOMMAND                      \
 115         "dhcp; "                                \
 116         "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; "         \
 117         "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; "       \
 118         "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; "     \
 119         "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; "                  \
 120         "bootm ${loadaddr} - ${dtbaddr}"
 121
 122 #define CONFIG_EXTRA_ENV_SETTINGS               \
 123         "autoload=no\0"                         \
 124         "ethaddr=00:01:90:00:C0:81\0"           \
 125         "dtbaddr=0x81000000\0"                  \
 126         "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0"  \
 127         "tftpdir=vladimir/oe/devkit3250\0"      \
 128         "userargs=oops=panic\0"
 129
 130 /*
 131  * U-Boot Commands
 132  */
 133
 134 /*
 135  * Boot Linux
 136  */
 137 #define CONFIG_CMDLINE_TAG
 138 #define CONFIG_SETUP_MEMORY_TAGS
 139
 140 #define CONFIG_BOOTFILE                 "uImage"
 141 #define CONFIG_LOADADDR                 0x80008000
 142
 143 /*
 144  * SPL specific defines
 145  */
 146 /* SPL will be executed at offset 0 */
 147
 148 /* SPL will use SRAM as stack */
 149 #define CONFIG_SPL_STACK                0x0000FFF8
 150
 151 /* Use the framework and generic lib */
 152
 153 /* SPL will use serial */
 154
 155 /* SPL loads an image from NAND */
 156 #define CONFIG_SPL_NAND_RAW_ONLY
 157
 158 #define CONFIG_SPL_NAND_SOFTECC
 159
 160 #define CONFIG_SPL_MAX_SIZE             0x20000
 161 #define CONFIG_SPL_PAD_TO               CONFIG_SPL_MAX_SIZE
 162
 163 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
 164 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 165 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x60000
 166
 167 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 168 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 169
 170 /* See common/spl/spl.c  spl_set_header_raw_uboot() */
 171 #define CONFIG_SYS_MONITOR_LEN          CONFIG_SYS_NAND_U_BOOT_SIZE
 172
 173 /*
 174  * Include SoC specific configuration
 175  */
 176 #include <asm/arch/config.h>
 177
 178 #endif  /* __CONFIG_DEVKIT3250_H__*/