include/configs/devkit3250.h

   1 /*
   2  * Embest/Timll DevKit3250 board configuration file
   3  *
   4  * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_DEVKIT3250_H__
  10 #define __CONFIG_DEVKIT3250_H__
  11
  12 /* SoC and board defines */
  13 #include <linux/sizes.h>
  14 #include <asm/arch/cpu.h>
  15
  16 #define CONFIG_MACH_TYPE                MACH_TYPE_DEVKIT3250
  17
  18 #define CONFIG_SYS_ICACHE_OFF
  19 #define CONFIG_SYS_DCACHE_OFF
  20 #if !defined(CONFIG_SPL_BUILD)
  21 #define CONFIG_SKIP_LOWLEVEL_INIT
  22 #endif
  23
  24 /*
  25  * Memory configurations
  26  */
  27 #define CONFIG_NR_DRAM_BANKS            1
  28 #define CONFIG_SYS_MALLOC_LEN           SZ_1M
  29 #define CONFIG_SYS_SDRAM_BASE           EMC_DYCS0_BASE
  30 #define CONFIG_SYS_SDRAM_SIZE           SZ_64M
  31 #define CONFIG_SYS_TEXT_BASE            0x83F00000
  32 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  33 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_TEXT_BASE - SZ_1M)
  34
  35 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  36
  37 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_4K \
  38                                          - GENERATED_GBL_DATA_SIZE)
  39
  40 /*
  41  * Serial Driver
  42  */
  43 #define CONFIG_SYS_LPC32XX_UART         5   /* UART5 */
  44
  45 /*
  46  * DMA
  47  */
  48 #if !defined(CONFIG_SPL_BUILD)
  49 #define CONFIG_DMA_LPC32XX
  50 #endif
  51
  52 /*
  53  * I2C
  54  */
  55 #define CONFIG_SYS_I2C
  56 #define CONFIG_SYS_I2C_LPC32XX
  57 #define CONFIG_SYS_I2C_SPEED            100000
  58
  59 /*
  60  * GPIO
  61  */
  62 #define CONFIG_LPC32XX_GPIO
  63
  64 /*
  65  * SSP/SPI
  66  */
  67 #define CONFIG_LPC32XX_SSP
  68 #define CONFIG_LPC32XX_SSP_TIMEOUT      100000
  69
  70 /*
  71  * Ethernet
  72  */
  73 #define CONFIG_RMII
  74 #define CONFIG_PHY_SMSC
  75 #define CONFIG_LPC32XX_ETH
  76 #define CONFIG_PHY_ADDR                 0x1F
  77 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  78
  79 /*
  80  * NOR Flash
  81  */
  82 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  83 #define CONFIG_SYS_MAX_FLASH_SECT       71
  84 #define CONFIG_SYS_FLASH_BASE           EMC_CS0_BASE
  85 #define CONFIG_SYS_FLASH_SIZE           SZ_4M
  86 #define CONFIG_SYS_FLASH_CFI
  87
  88 /*
  89  * NAND controller
  90  */
  91 #define CONFIG_NAND_LPC32XX_SLC
  92 #define CONFIG_SYS_NAND_BASE            SLC_NAND_BASE
  93 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  94 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  95
  96 /*
  97  * NAND chip timings
  98  */
  99 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS        14
 100 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH          66666666
 101 #define CONFIG_LPC32XX_NAND_SLC_WHOLD           200000000
 102 #define CONFIG_LPC32XX_NAND_SLC_WSETUP          50000000
 103 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS        14
 104 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH          66666666
 105 #define CONFIG_LPC32XX_NAND_SLC_RHOLD           200000000
 106 #define CONFIG_LPC32XX_NAND_SLC_RSETUP          50000000
 107
 108 #define CONFIG_SYS_NAND_BLOCK_SIZE              0x20000
 109 #define CONFIG_SYS_NAND_PAGE_SIZE               NAND_LARGE_BLOCK_PAGE_SIZE
 110 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 111
 112 /*
 113  * USB
 114  */
 115 #define CONFIG_USB_OHCI_LPC32XX
 116 #define CONFIG_USB_ISP1301_I2C_ADDR             0x2d
 117
 118 /*
 119  * U-Boot General Configurations
 120  */
 121 #define CONFIG_SYS_LONGHELP
 122 #define CONFIG_SYS_CBSIZE               1024
 123 #define CONFIG_SYS_PBSIZE               \
 124         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 125 #define CONFIG_SYS_MAXARGS              16
 126 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 127
 128 #define CONFIG_AUTO_COMPLETE
 129 #define CONFIG_CMDLINE_EDITING
 130
 131 /*
 132  * Pass open firmware flat tree
 133  */
 134
 135 /*
 136  * Environment
 137  */
 138 #define CONFIG_ENV_SIZE                 SZ_128K
 139 #define CONFIG_ENV_OFFSET               0x000A0000
 140
 141 #define CONFIG_BOOTCOMMAND                      \
 142         "dhcp; "                                \
 143         "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; "         \
 144         "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; "       \
 145         "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; "     \
 146         "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; "                  \
 147         "bootm ${loadaddr} - ${dtbaddr}"
 148
 149 #define CONFIG_EXTRA_ENV_SETTINGS               \
 150         "autoload=no\0"                         \
 151         "ethaddr=00:01:90:00:C0:81\0"           \
 152         "dtbaddr=0x81000000\0"                  \
 153         "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0"  \
 154         "tftpdir=vladimir/oe/devkit3250\0"      \
 155         "userargs=oops=panic\0"
 156
 157 /*
 158  * U-Boot Commands
 159  */
 160
 161 /*
 162  * Boot Linux
 163  */
 164 #define CONFIG_CMDLINE_TAG
 165 #define CONFIG_SETUP_MEMORY_TAGS
 166
 167 #define CONFIG_BOOTFILE                 "uImage"
 168 #define CONFIG_LOADADDR                 0x80008000
 169
 170 /*
 171  * SPL specific defines
 172  */
 173 /* SPL will be executed at offset 0 */
 174 #define CONFIG_SPL_TEXT_BASE            0x00000000
 175
 176 /* SPL will use SRAM as stack */
 177 #define CONFIG_SPL_STACK                0x0000FFF8
 178
 179 /* Use the framework and generic lib */
 180 #define CONFIG_SPL_FRAMEWORK
 181
 182 /* SPL will use serial */
 183
 184 /* SPL loads an image from NAND */
 185 #define CONFIG_SPL_NAND_SIMPLE
 186 #define CONFIG_SPL_NAND_RAW_ONLY
 187 #define CONFIG_SPL_NAND_DRIVERS
 188
 189 #define CONFIG_SPL_NAND_ECC
 190 #define CONFIG_SPL_NAND_SOFTECC
 191
 192 #define CONFIG_SPL_MAX_SIZE             0x20000
 193 #define CONFIG_SPL_PAD_TO               CONFIG_SPL_MAX_SIZE
 194
 195 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
 196 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 197 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x60000
 198
 199 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 200 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 201
 202 /* See common/spl/spl.c  spl_set_header_raw_uboot() */
 203 #define CONFIG_SYS_MONITOR_LEN          CONFIG_SYS_NAND_U_BOOT_SIZE
 204
 205 /*
 206  * Include SoC specific configuration
 207  */
 208 #include <asm/arch/config.h>
 209
 210 #endif  /* __CONFIG_DEVKIT3250_H__*/