1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Embest/Timll DevKit3250 board configuration file
5 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
8 #ifndef __CONFIG_DEVKIT3250_H__
9 #define __CONFIG_DEVKIT3250_H__
11 /* SoC and board defines */
12 #include <linux/sizes.h>
13 #include <asm/arch/cpu.h>
16 * Memory configurations
18 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
19 #define CONFIG_SYS_SDRAM_SIZE SZ_64M
21 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
22 - GENERATED_GBL_DATA_SIZE)
36 #define CONFIG_LPC32XX_ETH
37 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
42 #define CONFIG_SYS_MAX_FLASH_BANKS 1
43 #define CONFIG_SYS_MAX_FLASH_SECT 71
44 #define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE
45 #define CONFIG_SYS_FLASH_SIZE SZ_4M
50 #define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
51 #define CONFIG_SYS_MAX_NAND_DEVICE 1
52 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
57 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14
58 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666
59 #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000
60 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000
61 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14
62 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666
63 #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000
64 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000
69 #define CONFIG_USB_OHCI_LPC32XX
70 #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d
73 * U-Boot General Configurations
75 #define CONFIG_SYS_CBSIZE 1024
76 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
79 * Pass open firmware flat tree
86 #define CONFIG_EXTRA_ENV_SETTINGS \
88 "ethaddr=00:01:90:00:C0:81\0" \
89 "dtbaddr=0x81000000\0" \
90 "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \
91 "tftpdir=vladimir/oe/devkit3250\0" \
92 "userargs=oops=panic\0"
98 #define CONFIG_BOOTFILE "uImage"
101 * SPL specific defines
103 /* SPL will be executed at offset 0 */
105 /* SPL will use SRAM as stack */
106 #define CONFIG_SPL_STACK 0x0000FFF8
108 /* Use the framework and generic lib */
110 /* SPL will use serial */
112 /* SPL loads an image from NAND */
113 #define CONFIG_SPL_NAND_RAW_ONLY
115 #define CONFIG_SPL_NAND_SOFTECC
117 #define CONFIG_SPL_MAX_SIZE 0x20000
118 #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
120 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
121 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
123 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
124 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
126 /* See common/spl/spl.c spl_set_header_raw_uboot() */
127 #define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE
130 * Include SoC specific configuration
132 #include <asm/arch/config.h>
134 #endif /* __CONFIG_DEVKIT3250_H__*/