include/configs/devkit3250.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Embest/Timll DevKit3250 board configuration file
   4  *
   5  * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
   6  */
   7
   8 #ifndef __CONFIG_DEVKIT3250_H__
   9 #define __CONFIG_DEVKIT3250_H__
  10
  11 /* SoC and board defines */
  12 #include <linux/sizes.h>
  13 #include <asm/arch/cpu.h>
  14
  15 /*
  16  * Memory configurations
  17  */
  18 #define CONFIG_SYS_SDRAM_BASE           EMC_DYCS0_BASE
  19 #define CONFIG_SYS_SDRAM_SIZE           SZ_64M
  20
  21 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_4K \
  22                                          - GENERATED_GBL_DATA_SIZE)
  23
  24 /*
  25  * DMA
  26  */
  27
  28 /*
  29  * GPIO
  30  */
  31
  32 /*
  33  * Ethernet
  34  */
  35 #define CONFIG_RMII
  36 #define CONFIG_LPC32XX_ETH
  37 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  38
  39 /*
  40  * NOR Flash
  41  */
  42 #define CONFIG_SYS_MAX_FLASH_SECT       71
  43 #define CONFIG_SYS_FLASH_BASE           EMC_CS0_BASE
  44 #define CONFIG_SYS_FLASH_SIZE           SZ_4M
  45
  46 /*
  47  * NAND controller
  48  */
  49 #define CONFIG_SYS_NAND_BASE            SLC_NAND_BASE
  50 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  51 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  52
  53 /*
  54  * NAND chip timings
  55  */
  56 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS        14
  57 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH          66666666
  58 #define CONFIG_LPC32XX_NAND_SLC_WHOLD           200000000
  59 #define CONFIG_LPC32XX_NAND_SLC_WSETUP          50000000
  60 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS        14
  61 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH          66666666
  62 #define CONFIG_LPC32XX_NAND_SLC_RHOLD           200000000
  63 #define CONFIG_LPC32XX_NAND_SLC_RSETUP          50000000
  64
  65 /*
  66  * USB
  67  */
  68 #define CONFIG_USB_OHCI_LPC32XX
  69 #define CONFIG_USB_ISP1301_I2C_ADDR             0x2d
  70
  71 /*
  72  * U-Boot General Configurations
  73  */
  74 #define CONFIG_SYS_CBSIZE               1024
  75 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  76
  77 /*
  78  * Pass open firmware flat tree
  79  */
  80
  81 /*
  82  * Environment
  83  */
  84
  85 #define CONFIG_EXTRA_ENV_SETTINGS               \
  86         "autoload=no\0"                         \
  87         "ethaddr=00:01:90:00:C0:81\0"           \
  88         "dtbaddr=0x81000000\0"                  \
  89         "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0"  \
  90         "tftpdir=vladimir/oe/devkit3250\0"      \
  91         "userargs=oops=panic\0"
  92
  93 /*
  94  * U-Boot Commands
  95  */
  96
  97 /*
  98  * SPL specific defines
  99  */
 100 /* SPL will be executed at offset 0 */
 101
 102 /* SPL will use SRAM as stack */
 103 #define CONFIG_SPL_STACK                0x0000FFF8
 104
 105 /* Use the framework and generic lib */
 106
 107 /* SPL will use serial */
 108
 109 /* SPL loads an image from NAND */
 110 #define CONFIG_SPL_NAND_RAW_ONLY
 111
 112 #define CONFIG_SPL_NAND_SOFTECC
 113
 114 #define CONFIG_SPL_MAX_SIZE             0x20000
 115 #define CONFIG_SPL_PAD_TO               CONFIG_SPL_MAX_SIZE
 116
 117 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
 118 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x60000
 119
 120 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 121 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 122
 123 /* See common/spl/spl.c  spl_set_header_raw_uboot() */
 124 #define CONFIG_SYS_MONITOR_LEN          CONFIG_SYS_NAND_U_BOOT_SIZE
 125
 126 /*
 127  * Include SoC specific configuration
 128  */
 129 #include <asm/arch/config.h>
 130
 131 #endif  /* __CONFIG_DEVKIT3250_H__*/