1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
6 #ifndef _CONFIG_DB_MV7846MP_GP_H
7 #define _CONFIG_DB_MV7846MP_GP_H
10 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
11 * for DDR ECC byte filling in the SPL before loading the main
16 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
18 /* USB/EHCI configuration */
20 /* Environment in SPI NOR flash */
22 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
25 #define CONFIG_PCI_SCAN_SHOW
30 * mv-common.h should be defined after CMD configs since it used them
31 * to enable certain macros
33 #include "mv-common.h"
36 * Memory layout while starting into the bin_hdr via the
39 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
40 * 0x4000.4030 bin_hdr start address
41 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
42 * 0x4007.fffc BootROM stack top
44 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
45 * L2 cache thus cannot be used.
51 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
52 #define CONFIG_SPD_EEPROM 0x4e
54 #endif /* _CONFIG_DB_MV7846MP_GP_H */