2 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _CONFIG_DB_88F6720_H
8 #define _CONFIG_DB_88F6720_H
11 * High Level Configuration Options (easy to change)
13 #define CONFIG_DISPLAY_BOARDINFO_LATE
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
20 #define CONFIG_SYS_TEXT_BASE 0x00800000
21 #define CONFIG_SYS_TCLK 200000000 /* 200MHz */
24 * Commands configuration
28 #define CONFIG_SYS_I2C
29 #define CONFIG_SYS_I2C_MVTWSI
30 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
31 #define CONFIG_SYS_I2C_SLAVE 0x0
32 #define CONFIG_SYS_I2C_SPEED 100000
34 /* USB/EHCI configuration */
35 #define CONFIG_EHCI_IS_TDI
36 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
38 /* SPI NOR flash default params, used by sf commands */
39 #define CONFIG_SF_DEFAULT_SPEED 1000000
40 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
42 /* Environment in SPI NOR flash */
43 #define CONFIG_ENV_IS_IN_SPI_FLASH
44 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
45 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
46 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
48 #define CONFIG_PHY_MARVELL /* there is a marvell phy */
49 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
51 #define CONFIG_SYS_ALT_MEMTEST
53 /* Additional FS support/configuration */
54 #define CONFIG_SUPPORT_VFAT
57 * mv-common.h should be defined after CMD configs since it used them
58 * to enable certain macros
60 #include "mv-common.h"
63 * Memory layout while starting into the bin_hdr via the
66 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
67 * 0x4000.4030 bin_hdr start address
68 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
69 * 0x4007.fffc BootROM stack top
71 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
72 * L2 cache thus cannot be used.
77 #define CONFIG_SPL_FRAMEWORK
78 #define CONFIG_SPL_TEXT_BASE 0x40004030
79 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
81 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
82 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
84 #ifdef CONFIG_SPL_BUILD
85 #define CONFIG_SYS_MALLOC_SIMPLE
88 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
89 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
91 /* SPL related SPI defines */
92 #define CONFIG_SPL_SPI_LOAD
93 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
94 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
96 #endif /* _CONFIG_DB_88F6720_H */