2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #define CONFIG_SYS_NAND_LARGEPAGE
28 #define CONFIG_SYS_USE_NAND
29 #define CONFIG_DISPLAY_CPUINFO
30 #define MACH_TYPE_SCHMOOGIE 1255
31 #define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE
33 /*===================*/
34 /* SoC Configuration */
35 /*===================*/
36 #define CONFIG_ARM926EJS /* arm926ejs CPU core */
37 #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
38 #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
39 #define CONFIG_SYS_HZ 1000
40 #define CONFIG_SOC_DM644X
44 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
45 #define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
46 #define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
47 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
48 #define CONFIG_STACKSIZE (256*1024) /* regular stack */
49 #define PHYS_SDRAM_1 0x80000000 /* DDR Start */
50 #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
51 #define DDR_4BANKS /* 4-bank DDR2 (128MB) */
52 /*====================*/
53 /* Serial Driver info */
54 /*====================*/
55 #define CONFIG_SYS_NS16550
56 #define CONFIG_SYS_NS16550_SERIAL
57 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
58 #define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
59 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
60 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
61 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
62 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
63 /*===================*/
64 /* I2C Configuration */
65 /*===================*/
66 #define CONFIG_HARD_I2C
67 #define CONFIG_DRIVER_DAVINCI_I2C
68 #define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
69 #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
70 /*==================================*/
71 /* Network & Ethernet Configuration */
72 /*==================================*/
73 #define CONFIG_DRIVER_TI_EMAC
75 #define CONFIG_BOOTP_DEFAULT
76 #define CONFIG_BOOTP_DNS
77 #define CONFIG_BOOTP_DNS2
78 #define CONFIG_BOOTP_SEND_HOSTNAME
79 #define CONFIG_NET_RETRY_COUNT 10
80 #define CONFIG_OVERWRITE_ETHADDR_ONCE
81 /*=====================*/
82 /* Flash & Environment */
83 /*=====================*/
84 #undef CONFIG_ENV_IS_IN_FLASH
85 #define CONFIG_SYS_NO_FLASH
86 #define CONFIG_NAND_DAVINCI
87 #define CONFIG_SYS_NAND_CS 2
88 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
89 #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
90 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
91 #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
92 #define CONFIG_SYS_NAND_BASE 0x02000000
93 #define CONFIG_SYS_NAND_HW_ECC
94 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
95 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
96 /*=====================*/
97 /* Board related stuff */
98 /*=====================*/
99 #define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */
100 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */
101 #define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */
102 #define CONFIG_SYS_UID_ADDR 0x50 /* UID chip I2C address */
103 /*==============================*/
104 /* U-Boot general configuration */
105 /*==============================*/
106 #undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
107 #define CONFIG_MISC_INIT_R
108 #undef CONFIG_BOOTDELAY
109 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
110 #define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
111 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
112 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
113 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
114 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
115 #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
116 #define CONFIG_VERSION_VARIABLE
117 #define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
118 #define CONFIG_SYS_HUSH_PARSER
119 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
120 #define CONFIG_CMDLINE_EDITING
121 #define CONFIG_SYS_LONGHELP
122 #define CONFIG_CRC32_VERIFY
123 #define CONFIG_MX_CYCLIC
124 /*===================*/
125 /* Linux Information */
126 /*===================*/
127 #define LINUX_BOOT_PARAM_ADDR 0x80000100
128 #define CONFIG_CMDLINE_TAG
129 #define CONFIG_SETUP_MEMORY_TAGS
130 #define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
131 #define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
132 /*=================*/
133 /* U-Boot commands */
134 /*=================*/
135 #include <config_cmd_default.h>
136 #define CONFIG_CMD_ASKENV
137 #define CONFIG_CMD_DHCP
138 #define CONFIG_CMD_DIAG
139 #define CONFIG_CMD_I2C
140 #define CONFIG_CMD_MII
141 #define CONFIG_CMD_PING
142 #define CONFIG_CMD_SAVES
143 #define CONFIG_CMD_DATE
144 #define CONFIG_CMD_NAND
145 #undef CONFIG_CMD_EEPROM
146 #undef CONFIG_CMD_BDI
147 #undef CONFIG_CMD_FPGA
148 #undef CONFIG_CMD_SETGETDCR
149 #undef CONFIG_CMD_FLASH
150 #undef CONFIG_CMD_IMLS
152 #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
154 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
155 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
156 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
157 CONFIG_SYS_INIT_RAM_SIZE - \
158 GENERATED_GBL_DATA_SIZE)
160 #endif /* __CONFIG_H */