2 * Copyright (C) 2009 Texas Instruments Incorporated
4 * SPDX-License-Identifier: GPL-2.0+
10 /* Spectrum Digital TMS320DM6467 EVM board */
11 #define DAVINCI_DM6467EVM
12 #define CONFIG_SYS_USE_NAND
13 #define CONFIG_SYS_NAND_SMALLPAGE
15 #define CONFIG_SKIP_LOWLEVEL_INIT
17 /* SoC Configuration */
18 #define CONFIG_ARM926EJS /* arm926ejs CPU */
20 /* Clock rates detection */
22 extern unsigned int davinci_arm_clk_get(void);
25 /* Arm Clock frequency */
26 #define CONFIG_SYS_CLK_FREQ davinci_arm_clk_get()
27 /* Timer Input clock freq */
28 #define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2)
29 #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
30 #define CONFIG_SOC_DM646X
32 /* EEPROM definitions for EEPROM */
33 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
34 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
35 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
36 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
39 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
40 #define CONFIG_SYS_MEMTEST_START 0x80000000
41 #define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
42 #define CONFIG_NR_DRAM_BANKS 1
43 #define PHYS_SDRAM_1 0x80000000 /* DDR Start */
44 #define PHYS_SDRAM_1_SIZE (256 << 20) /* DDR size 256MB */
46 /* Linux interfacing */
47 #define CONFIG_CMDLINE_TAG
48 #define CONFIG_SETUP_MEMORY_TAGS
49 #define CONFIG_SYS_BARGSIZE 1024 /* Bootarg Size */
50 #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
51 #define CONFIG_REVISION_TAG
53 /* Serial Driver info */
54 #define CONFIG_SYS_NS16550
55 #define CONFIG_SYS_NS16550_SERIAL
56 #define CONFIG_SYS_NS16550_REG_SIZE 4
57 #define CONFIG_SYS_NS16550_COM1 0x01c20000
58 #define CONFIG_SYS_NS16550_CLK 24000000
59 #define CONFIG_CONS_INDEX 1
60 #define CONFIG_BAUDRATE 115200
62 /* I2C Configuration */
63 #define CONFIG_SYS_I2C
64 #define CONFIG_SYS_I2C_DAVINCI
65 #define CONFIG_SYS_DAVINCI_I2C_SPEED 80000
66 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10
68 /* Network & Ethernet Configuration */
69 #define CONFIG_DRIVER_TI_EMAC
71 #define CONFIG_BOOTP_DNS
72 #define CONFIG_BOOTP_DNS2
73 #define CONFIG_BOOTP_SEND_HOSTNAME
74 #define CONFIG_NET_RETRY_COUNT 10
75 #define CONFIG_CMD_NET
77 /* Flash & Environment */
78 #define CONFIG_SYS_NO_FLASH
79 #ifdef CONFIG_SYS_USE_NAND
80 #define CONFIG_NAND_DAVINCI
81 #define CONFIG_SYS_NAND_MASK_CLE 0x80000
82 #define CONFIG_SYS_NAND_MASK_ALE 0x40000
83 #define CONFIG_SYS_NAND_CS 2
84 #undef CONFIG_ENV_IS_IN_FLASH
85 #define CONFIG_ENV_IS_IN_NAND
86 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
87 #define CONFIG_SYS_NAND_BASE_LIST {0x42000000, }
88 #define CONFIG_SYS_NAND_HW_ECC
89 #define CONFIG_SYS_MAX_NAND_DEVICE 1
90 #define CONFIG_ENV_OFFSET 0
92 #define CONFIG_ENV_IS_NOWHERE
93 #define CONFIG_ENV_SIZE (4 << 10) /* 4 KiB */
96 /* U-Boot general configuration */
97 #define CONFIG_BOOTDELAY 3
98 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
99 #define CONFIG_SYS_PROMPT "DM6467 EVM > " /* Monitor Command Prompt */
100 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
101 #define CONFIG_SYS_PBSIZE \
102 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
103 #define CONFIG_SYS_MAXARGS 16
104 #define CONFIG_VERSION_VARIABLE
105 #define CONFIG_AUTO_COMPLETE
106 #define CONFIG_SYS_HUSH_PARSER
107 #define CONFIG_CMDLINE_EDITING
108 #define CONFIG_SYS_LONGHELP
109 #define CONFIG_CRC32_VERIFY
110 #define CONFIG_MX_CYCLIC
111 #define CONFIG_BOOTCOMMAND "source 0x82080000; dhcp; bootm"
112 #define CONFIG_BOOTARGS \
113 "mem=120M console=ttyS0,115200n8 " \
114 "root=/dev/hda1 rw noinitrd ip=dhcp"
116 /* U-Boot commands */
117 #include <config_cmd_default.h>
118 #define CONFIG_CMD_ASKENV
119 #define CONFIG_CMD_DIAG
120 #define CONFIG_CMD_I2C
121 #define CONFIG_CMD_MII
122 #define CONFIG_CMD_SAVES
123 #define CONFIG_CMD_EEPROM
124 #define CONFIG_CMD_PING
125 #define CONFIG_CMD_DHCP
126 #undef CONFIG_CMD_BDI
127 #undef CONFIG_CMD_FPGA
128 #undef CONFIG_CMD_SETGETDCR
129 #ifdef CONFIG_SYS_USE_NAND
130 #undef CONFIG_CMD_FLASH
131 #undef CONFIG_CMD_IMLS
132 #define CONFIG_CMD_NAND
135 #ifdef CONFIG_CMD_BDI
136 #define CONFIG_CLOCKS
139 #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
141 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
142 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
143 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
144 CONFIG_SYS_INIT_RAM_SIZE - \
145 GENERATED_GBL_DATA_SIZE)
147 #endif /* __CONFIG_H */