include/configs/da850evm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16
  17 /*
  18  * SoC Configuration
  19  */
  20 #ifndef __ASSEMBLY__
  21 unsigned long get_board_sys_clk(void);
  22 #endif
  23 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  24 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  25 #define CONFIG_SYS_OSCIN_FREQ           24000000
  26 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  27 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  28
  29 #ifdef CONFIG_MTD_NOR_FLASH
  30 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  31 #endif
  32
  33 /*
  34  * Memory Info
  35  */
  36 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  37 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  38 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  39 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
  40 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
  41 /* memtest start addr */
  42
  43 /* memtest will be run on 16MB */
  44
  45 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  46         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  47         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  48         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  49         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  50         DAVINCI_SYSCFG_SUSPSRC_I2C)
  51
  52 /*
  53  * PLL configuration
  54  */
  55
  56 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  57 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  58
  59 /*
  60  * DDR2 memory configuration
  61  */
  62 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  63                                         DV_DDR_PHY_EXT_STRBEN | \
  64                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  65
  66 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  67         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
  68         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  69         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  70         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  71         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  72         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  73         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  74
  75 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  76 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  77
  78 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  79         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  80         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  81         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  82         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  83         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  84         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
  85         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
  86         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
  87
  88 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
  89         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
  90         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
  91         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
  92         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
  93         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
  94         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
  95         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
  96
  97 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
  98 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
  99
 100 /*
 101  * Serial Driver info
 102  */
 103 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 104
 105 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 106
 107 /*
 108  * I2C Configuration
 109  */
 110 #ifndef CONFIG_SPL_BUILD
 111 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 112 #endif
 113
 114 /*
 115  * Flash & Environment
 116  */
 117 #ifdef CONFIG_MTD_RAW_NAND
 118 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 119 #define CONFIG_SYS_NAND_PAGE_2K
 120 #define CONFIG_SYS_NAND_CS              3
 121 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 122 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 123 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 124 #undef CONFIG_SYS_NAND_HW_ECC
 125 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 126 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 127 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x40000
 128 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 129 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 130 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 131                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 132                                         CONFIG_SYS_MALLOC_LEN -       \
 133                                         GENERATED_GBL_DATA_SIZE)
 134 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 135                                 24, 25, 26, 27, 28, \
 136                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 137                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 138                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 139                                 59, 60, 61, 62, 63 }
 140 #define CONFIG_SYS_NAND_ECCSIZE         512
 141 #define CONFIG_SYS_NAND_ECCBYTES        10
 142 #endif
 143
 144 /*
 145  * Network & Ethernet Configuration
 146  */
 147 #ifdef CONFIG_DRIVER_TI_EMAC
 148 #define CONFIG_NET_RETRY_COUNT  10
 149 #endif
 150
 151 #ifdef CONFIG_MTD_NOR_FLASH
 152 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
 153 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 154 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 155 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 156 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 157                + 3)
 158 #endif
 159
 160 /*
 161  * U-Boot general configuration
 162  */
 163 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 164 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 165 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 166
 167 /*
 168  * Linux Information
 169  */
 170 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 171 #define CONFIG_HWCONFIG         /* enable hwconfig */
 172
 173 #define DEFAULT_LINUX_BOOT_ENV \
 174         "loadaddr=0xc0700000\0" \
 175         "fdtaddr=0xc0600000\0" \
 176         "scriptaddr=0xc0600000\0"
 177
 178 #include <environment/ti/mmc.h>
 179
 180 #define CONFIG_EXTRA_ENV_SETTINGS \
 181         DEFAULT_LINUX_BOOT_ENV \
 182         DEFAULT_MMC_TI_ARGS \
 183         "bootpart=0:2\0" \
 184         "bootdir=/boot\0" \
 185         "bootfile=zImage\0" \
 186         "fdtfile=da850-evm.dtb\0" \
 187         "boot_fdt=yes\0" \
 188         "boot_fit=0\0" \
 189         "console=ttyS2,115200n8\0" \
 190         "hwconfig=dsp:wake=yes"
 191
 192 #ifdef CONFIG_CMD_BDI
 193 #define CONFIG_CLOCKS
 194 #endif
 195
 196 /* USB Configs */
 197 #define CONFIG_USB_OHCI_NEW
 198 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 199
 200 #ifndef CONFIG_MTD_NOR_FLASH
 201 #define CONFIG_SPL_PAD_TO       32768
 202 #endif
 203
 204 #ifdef CONFIG_SPL_BUILD
 205 /* defines for SPL */
 206 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 207                                                 CONFIG_SYS_MALLOC_LEN)
 208 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 209 #define CONFIG_SPL_STACK        0x8001ff00
 210 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 211
 212 #endif
 213
 214 /* Load U-Boot Image From MMC */
 215
 216 /* additions for new relocation code, must added to all boards */
 217 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 218
 219 #ifdef CONFIG_MTD_NOR_FLASH
 220 #define CONFIG_SYS_INIT_SP_ADDR         0x8001ff00
 221 #else
 222 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 223                                         GENERATED_GBL_DATA_SIZE)
 224 #endif /* CONFIG_MTD_NOR_FLASH */
 225
 226 #include <asm/arch/hardware.h>
 227
 228 #endif /* __CONFIG_H */