include/configs/da850evm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16 /* check if direct NOR boot config is used */
  17 #ifndef CONFIG_DIRECT_NOR_BOOT
  18 #define CONFIG_USE_SPIFLASH
  19 #endif
  20
  21 /*
  22  * SoC Configuration
  23  */
  24 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  25 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  26 #define CONFIG_SYS_OSCIN_FREQ           24000000
  27 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  28 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  29 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  30
  31 #ifdef CONFIG_DIRECT_NOR_BOOT
  32 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  33 #endif
  34
  35 /*
  36  * Memory Info
  37  */
  38 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  39 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  40 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  41 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  42 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
  43 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
  44 /* memtest start addr */
  45
  46 /* memtest will be run on 16MB */
  47
  48 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  49         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  50         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  51         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  52         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  53         DAVINCI_SYSCFG_SUSPSRC_I2C)
  54
  55 /*
  56  * PLL configuration
  57  */
  58
  59 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  60 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  61
  62 /*
  63  * DDR2 memory configuration
  64  */
  65 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  66                                         DV_DDR_PHY_EXT_STRBEN | \
  67                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  68
  69 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  70         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
  71         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  72         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  73         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  74         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  75         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  76         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  77
  78 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  79 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  80
  81 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  82         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  83         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  84         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  85         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  86         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  87         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
  88         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
  89         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
  90
  91 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
  92         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
  93         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
  94         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
  95         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
  96         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
  97         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
  98         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
  99
 100 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
 101 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
 102
 103 /*
 104  * Serial Driver info
 105  */
 106 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 107
 108 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 109
 110 #ifdef CONFIG_USE_SPIFLASH
 111 #define CONFIG_SYS_SPI_U_BOOT_SIZE      0x40000
 112 #endif
 113
 114 /*
 115  * I2C Configuration
 116  */
 117 #ifndef CONFIG_SPL_BUILD
 118 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 119 #endif
 120
 121 /*
 122  * Flash & Environment
 123  */
 124 #ifdef CONFIG_MTD_RAW_NAND
 125 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 126 #define CONFIG_SYS_NAND_PAGE_2K
 127 #define CONFIG_SYS_NAND_CS              3
 128 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 129 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 130 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 131 #undef CONFIG_SYS_NAND_HW_ECC
 132 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 133 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 134 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 135 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
 136 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 137 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x40000
 138 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 139 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 140 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 141                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 142                                         CONFIG_SYS_MALLOC_LEN -       \
 143                                         GENERATED_GBL_DATA_SIZE)
 144 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 145                                 24, 25, 26, 27, 28, \
 146                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 147                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 148                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 149                                 59, 60, 61, 62, 63 }
 150 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 151 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 152 #define CONFIG_SYS_NAND_ECCSIZE         512
 153 #define CONFIG_SYS_NAND_ECCBYTES        10
 154 #define CONFIG_SYS_NAND_OOBSIZE         64
 155 #define CONFIG_SPL_NAND_BASE
 156 #define CONFIG_SPL_NAND_DRIVERS
 157 #define CONFIG_SPL_NAND_ECC
 158 #define CONFIG_SPL_NAND_LOAD
 159
 160 #ifndef CONFIG_SPL_BUILD
 161 #define CONFIG_SYS_NAND_SELF_INIT
 162 #endif
 163 #endif
 164
 165 /*
 166  * Network & Ethernet Configuration
 167  */
 168 #ifdef CONFIG_DRIVER_TI_EMAC
 169 #define CONFIG_BOOTP_DNS2
 170 #define CONFIG_BOOTP_SEND_HOSTNAME
 171 #define CONFIG_NET_RETRY_COUNT  10
 172 #endif
 173
 174 #ifdef CONFIG_USE_NOR
 175 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
 176 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 177 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 178 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 179 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 180                + 3)
 181 #endif
 182
 183 /*
 184  * U-Boot general configuration
 185  */
 186 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 187 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 188 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 189 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 190
 191 /*
 192  * Linux Information
 193  */
 194 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 195 #define CONFIG_HWCONFIG         /* enable hwconfig */
 196 #define CONFIG_CMDLINE_TAG
 197 #define CONFIG_REVISION_TAG
 198 #define CONFIG_SETUP_MEMORY_TAGS
 199
 200 #define CONFIG_BOOTCOMMAND \
 201                 "run envboot; " \
 202                 "run mmcboot; "
 203
 204 #define DEFAULT_LINUX_BOOT_ENV \
 205         "loadaddr=0xc0700000\0" \
 206         "fdtaddr=0xc0600000\0" \
 207         "scriptaddr=0xc0600000\0"
 208
 209 #include <environment/ti/mmc.h>
 210
 211 #define CONFIG_EXTRA_ENV_SETTINGS \
 212         DEFAULT_LINUX_BOOT_ENV \
 213         DEFAULT_MMC_TI_ARGS \
 214         "bootpart=0:2\0" \
 215         "bootdir=/boot\0" \
 216         "bootfile=zImage\0" \
 217         "fdtfile=da850-evm.dtb\0" \
 218         "boot_fdt=yes\0" \
 219         "boot_fit=0\0" \
 220         "console=ttyS2,115200n8\0" \
 221         "hwconfig=dsp:wake=yes"
 222
 223 #ifdef CONFIG_CMD_BDI
 224 #define CONFIG_CLOCKS
 225 #endif
 226
 227 #if !defined(CONFIG_MTD_RAW_NAND) && \
 228         !defined(CONFIG_USE_NOR) && \
 229         !defined(CONFIG_USE_SPIFLASH)
 230 #endif
 231
 232 /* USB Configs */
 233 #define CONFIG_USB_OHCI_NEW
 234 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 235
 236 #ifndef CONFIG_DIRECT_NOR_BOOT
 237 /* defines for SPL */
 238 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 239                                                 CONFIG_SYS_MALLOC_LEN)
 240 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 241 #define CONFIG_SPL_STACK        0x8001ff00
 242 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 243 #define CONFIG_SPL_PAD_TO       32768
 244 #endif
 245
 246 /* Load U-Boot Image From MMC */
 247
 248 /* additions for new relocation code, must added to all boards */
 249 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 250
 251 #ifdef CONFIG_DIRECT_NOR_BOOT
 252 #define CONFIG_SYS_INIT_SP_ADDR         0x8001ff00
 253 #else
 254 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 255                                         GENERATED_GBL_DATA_SIZE)
 256 #endif /* CONFIG_DIRECT_NOR_BOOT */
 257
 258 #include <asm/arch/hardware.h>
 259
 260 #endif /* __CONFIG_H */